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Is the thermal impedance from a GPU's wafer to the heatsink low enough that you could get close to doubling the clock speed if you halved the duty-cycle (render 50% of the full-TDP framerate).

An assumptions I've made through research is that the TDP (joules per second of thermal dissipation capacity) is highly related to the amount of work a GPU can do per unit time.

This capability at some degree is made apparent by reference to the "boost" modes and thermal dissipation schemes of today's high-power GPUs.

I do realize that this is probably not a linear relationship, but I'm talking very small bursts of work at the higher frequency:

Say a card can render a specific frame in 16ms continuously at its TDP, that's 60fps. I want to instead render that same frame in 8ms and then skip a frame, repeat (or maybe 6ms if I skip 2 frames?)

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  • \$\begingroup\$ I don't see the point. If you're doing less then run at a lower frequency, and if you need more speed then increase the clock speed dynamically. \$\endgroup\$ – Ignacio Vazquez-Abrams Aug 14 '16 at 16:53
  • \$\begingroup\$ "... if you halved the duty-cycle (render 50% of the full-TDP framerate)." What does that sentence mean? \$\endgroup\$ – Transistor Aug 14 '16 at 17:01
  • \$\begingroup\$ @IgnacioVazquez-Abrams One reason I'm noodling on this: can you scale on-time frequency more drastically if you spend drastic amounts of time sleeping (also giving the heatsink more time to dissipate work-latent heat between bursts). \$\endgroup\$ – joshperry Aug 14 '16 at 17:19
  • \$\begingroup\$ @Transistor I added an empirical example to the question to help clarify. \$\endgroup\$ – joshperry Aug 14 '16 at 17:20
  • \$\begingroup\$ Sleeping can only give you integral period increments whereas clock scaling can give you a very large number of fractional period increments, leading to overall more consistent performance. \$\endgroup\$ – Ignacio Vazquez-Abrams Aug 14 '16 at 17:26
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Probably not.

First of all TDP doesn't linearily scale with clock speed, a doubling in clock speed might triple or quadruple or even further increase the heat produced.

Secondly, heat is not the only limiting factor of clock speed. The signal still has to reach its destination inside the IC within a limited time and the logic gates and traces add latency. If you increase clock speed enough, without changing the GPU physically, the signal won't travel fast enough and the logic circuit won't function properly.

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  • \$\begingroup\$ I'm hoping to deal with nonlinear scaling through hardware interleaving. But I'd like the amount of work done during each node's on-time to be as high as possible. \$\endgroup\$ – joshperry Aug 14 '16 at 17:49
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The power consumed by CMOS circuits, including GPU's, is primarily switching power. This occurs when a node transitions from a high to low / low to high logic level, due to all the capacitance associated with that node (output cap, input cap to further logic gates, parasitic caps, wire caps, etc) having to swing up or down as well. Once the node has switched, there is, relative to the switching event, no power consumed. Only leakage currents through the 'OFF' FET's contribute to power here, but this is orders of magnitude lower than the switching event.

So reducing the duty cycle is not going to help in this case.

In fact, because the circuit is most likely bound by flip flops, reducing the duty cycle will not even make a difference in the heat producing circuit. Your rising edge of clock is used to latch values, and the low duty cycle is staticized into a steady signal for the circuit blocks. This happens because most memory elements output is triggered at each clock edge.

Furthermore, logic blocks have a delay. Say 300ps. No matter how shortly you pulse your inputs, the delay is 300ps. So changing the duty cycle will not help with this either.

And, if your clock makes it to the actual launching flip flops, if the pulse is not sufficiently long (regardless of the frequency between pulses), the transmission element into the first latch will not remain open long enough for any data to be written into the bitnode (setup or hold violation). You can see this in the image below, as the red/blue bars around the rising edge of the clock signal.

setuphold

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No. And here's a list of reasons:
A "powerwall" exists where you need to actually double the power if you want to double the speed. This is because you hit velocity saturation before you get out of subthreshold at current feature sizes (~25nm). This just means you cannot push transistors faster assuming you already designed for speed.

The best "gain" you can get with CMOS is 70mv/decade of current. This means that if you want mail something faster, again, you need to do more concurrently. To make an IC go "faster", you end up increasing the threshold and thereby increasing the leakage. For "fast" designs, you have almost the same power consumed dynamically during the switch transition as you during the integrated time between switching events.

GPUs are designed to run at 60FPS, and then you sleep to dissipate heat. You are limited by the thermal transfer. If you increased the switching cycle speed, you'd still have to cut back on transistors to hit your heat target.

If you want a TDP survey for power, there's my 2015 results: Powerwall The complete references with a quick writeup are here.
The best way to make something go twice as fast is to 1/2 the amount of code you send through it.

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  • \$\begingroup\$ Very very interesting, thank you for the excellent information! \$\endgroup\$ – joshperry Aug 15 '16 at 4:07

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