This is a relatively big subject but here is an overview. It depends what your maximum frequency is. If your frequency is not too high you can use counters.
The secret for a good reset counter is to parameterize it with respect to the frequency. You can write it in such a way that you put in the following parameters: frequency as a float, delay required also a float. The synthesizer can then take care of the required count. This can work for higher frequencies than you think. A 16-bit counter is not that big.
If you are after the maximum clock frequency possible, linear feedback shift registers(LFSRs) are your solution. LUTs in FPGAs have a carry chain like this:
You utilize this when you use LFSRs. An LFSR has the following structure:
You have a characteristic polynomial, which determines if there is an XOR gate between two stages. Something like: if 1 place XOR, if 0 connect directly. It then generates a pattern that is not sequential, but is always the same length.
LFSRs are fast because you have 1 LUT propagation delay at most. In counters, i.e. adders, the carry needs to propagate through all the LUTs. LFSRs also connect directly to the adjacent LUT through the carry chain.