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What is the best way to implement a timeout, written in VHDL?

The purpose of this is to reset a state machine to an IDLE state if a certain amount of time has passed (a few seconds at most), to avoid a deadlock. The only thing that come to my mind is a nasty clock counter with a big integer range but my concern is LUTs usage and optimization here. And I'm assuming my FPGA might have trouble fitting the logic of a 16 bit integer counter at full speed

Thanks for your help

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  • \$\begingroup\$ Would be nice if, instead of downvoting and leaving, you'd leave me a comment to work with... \$\endgroup\$ – Fluffy Aug 15 '16 at 11:11
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Here's a flexible pattern I've used a lot for this and similar purposes.

I prefer to use the actual clock period and delay values to generate the count values, rather than calculating magic numbers.

It will generate a counter - but a 16 bit counter is invisibly small in any FPGA you're likely to find today. Beyond about 24 bits it may start to impact speed, then you can break it into two smaller counters, using the first as a prescaler, generating a clock enable for the second.

And the pattern shown re-uses the same counter, to matter how many different delay values you need - unless you need more than one delay simultaneously.

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This is a relatively big subject but here is an overview. It depends what your maximum frequency is. If your frequency is not too high you can use counters.

The secret for a good reset counter is to parameterize it with respect to the frequency. You can write it in such a way that you put in the following parameters: frequency as a float, delay required also a float. The synthesizer can then take care of the required count. This can work for higher frequencies than you think. A 16-bit counter is not that big.

If you are after the maximum clock frequency possible, linear feedback shift registers(LFSRs) are your solution. LUTs in FPGAs have a carry chain like this: carry chai You utilize this when you use LFSRs. An LFSR has the following structure: lfsr You have a characteristic polynomial, which determines if there is an XOR gate between two stages. Something like: if 1 place XOR, if 0 connect directly. It then generates a pattern that is not sequential, but is always the same length.

LFSRs are fast because you have 1 LUT propagation delay at most. In counters, i.e. adders, the carry needs to propagate through all the LUTs. LFSRs also connect directly to the adjacent LUT through the carry chain.

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  • \$\begingroup\$ Thank you very much for your input, I didn't know about LFSRs, this is something I'll keep in mind for a further iteration of my design probably. I didn't estimate the capabilities of my FPGA precisely enough, counters will do \$\endgroup\$ – Fluffy Aug 15 '16 at 11:58

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