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I tried to do a monte carlo analysis of the opamp that I have designed. I ran the simulation for 100 samples with matching and process, suprisingly the results I get are very bizare. I have gains that are not even 1 dB which is something I completely dint see with a normal corner/process variation . I know that the reason for this bizare result is that the simulation takes mismatch into account(shown in image below with the configured simulation).But my main question is how can I improve this result keeping my design as it is ? IS there a way through which I could tune my MOSFET dimensions such that I have imrpoved results ?

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Simulation Configuration

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Simulation results with mismatch included as shown in the simulation configuration.

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Simulation result without mismatch but with only process.

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Circuit diagram, with the resistor divider being the outputs from the bandgap reference.

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    \$\begingroup\$ I have a feeling taht tweaking transistors won't help and you're missing the point. Simulate a couple of the worse corner cases, find the problem - such as, stages biassed hard into saturation or completely off - and fix the circuit first. \$\endgroup\$ – Brian Drummond Aug 15 '16 at 20:15
  • \$\begingroup\$ @BrianDrummond Okay,yes I think I need to do that.But thats gonna be really hard I guess. When I do corners I see the DC gain reducing from the nominal,they range from 40dB to 85 dB but they never go below 0dB. But when I include mismatch then it totally a different result. May be I should increase the lengths such that process variation takes a lesser toll. Currently my min length is 1um (process minimum is 0.350 um). Let me try then ! \$\endgroup\$ – Bhuvanesh Narayanan Aug 15 '16 at 20:22
  • \$\begingroup\$ @BrianDrummond Now I have also included the process variation result without mismatch considered. \$\endgroup\$ – Bhuvanesh Narayanan Aug 15 '16 at 20:37
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    \$\begingroup\$ Why don't you share the circuit? \$\endgroup\$ – Alper91 Aug 15 '16 at 20:50
  • \$\begingroup\$ @Alper91 Yup I should have, will include that too. it a bit big with bandgap so thought it might be a bit too much. But yeah it should not be that hard. I will include it now. \$\endgroup\$ – Bhuvanesh Narayanan Aug 15 '16 at 20:54
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Most likely the problem is not your design but the testbench that you are using. The low gain and the high-pass behavior of your simulations suggest that the operational amplifier does not work properly, because the DC operating point is not set correctly.

You need to make sure that DC operating point is such that your input signal is within the input common range of the opamp and the output signal is not too high. With an offset in the range of a few mV and a gain in the order of 60dB or more this can happen quite easily.

The Monte-Carlo simulation is done with a fixed seed. So you will get the same results whenever you run a simulation. This helps to isolate the problem. Pick a run which is completely off and resimulate only this run. Check the DC operating point and fix your testbench.

This can be done by setting "Starting Run Number" to the number of the run you want to simulate and setting the "Number of Points" to one.

Update: After looking at the schematic I am sure that it is the testbench (or the lack thereof). As a quick fix you could feed back the ouput to the inverting input using a low pass filter with a cut-off frequency that is very low. Then you should make a real testbench.

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  • \$\begingroup\$ Ah ok. I think that when I do a process/corner simulation all the NMOS go in the same corner. But when I include mismatch to my monte carlo then the diffntial gain caused because of the mismatch between the NMOS's is big enough that the output hits the rail. So the mismatch induced differential gain for a common mode signal is triggering ths issue I guess.Bcaus I am using the same DC source for both the command mode signal which means they have the same comman mode voltage which is according to the deisng. And one of the DC source has AC magnitude of 1V so that I can look into the AC analysis. \$\endgroup\$ – Bhuvanesh Narayanan Aug 15 '16 at 21:18
  • \$\begingroup\$ I will try with the starting run number method that you had suggested. I could understand a bit further with that. \$\endgroup\$ – Bhuvanesh Narayanan Aug 15 '16 at 21:20
  • \$\begingroup\$ With MC analysis you basically generate a small DC input voltage, but you have no testbench that takes care of that. Because of that input voltage your opamp saturates. With process variation there is no offset, because all transistors (of the same kind) change the same way. \$\endgroup\$ – Mario Aug 15 '16 at 21:25
  • \$\begingroup\$ But if I feedback the output to the inverting stage then wouldnt it form a source follower with a gain of 1 ? \$\endgroup\$ – Bhuvanesh Narayanan Aug 15 '16 at 21:27
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    \$\begingroup\$ Right! But there is no DC in an AC simulation only small frequencies. The behavior of the filter should be visible at low frequencies. \$\endgroup\$ – Mario Aug 15 '16 at 21:57
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Your biasing network is very sensitive to V_th, as you are directly feeding a bias voltage into your circuit (as opposed to a bias current). Try feeding net063 and net0142 with current mirrors instead.

Also, some processes will give you ranges of variation based on the distance between transistors. sometimes Monte-Carlo can be set up to give you lot-lot variation, which probably is a bit overkill for common-centroid transistors. Read your design manual.

And name your nets something proper. Nobody wants to go around tracking down net0142.

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  • \$\begingroup\$ Sure, I also removed the bandgap and simulated with only a voltage source but I still get the same response. Yeah could also be that the simulation takes mismatch too much into account because then the differential gain for a comman mode signal is too high. \$\endgroup\$ – Bhuvanesh Narayanan Aug 15 '16 at 21:23
  • \$\begingroup\$ Your Monte-Carlo results aren't wrong because they look bad - you must find out what "normal" variation should be first. Your variation is so bad because you are biasing MOSFETs using a fixed voltage, not because your bandgap reference is bad. \$\endgroup\$ – W5VO Aug 15 '16 at 21:28
  • \$\begingroup\$ Yes now I get it ! It was this DC voltage induced through the variation that was saturating the output. \$\endgroup\$ – Bhuvanesh Narayanan Aug 15 '16 at 21:51

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