Nano capacitors in RAM act as leak bucket and continuously lose charge. For this RAM has to be refreshed periodically in order to charge those nano-capacitors again. "During the refresh cycles memory controller reads the data of each cell and recharge it". This thing puts me in doubt. If memory controller reads data during RAM refresh cycle then that data has to be stored temporarily in somewhere else. Suppose I've 4GB RAM and 80% RAM is being used. "So memory controller requires atleast 2GB space to temporarily store data of RAM during its refresh cycles". Does memory controller also have its own memory? If memory controller reads data then who writes it after refresh? I used to think that "sense amplifiers" are used to read and write data in each column of RAM.

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    \$\begingroup\$ Probably should clarify that you are talking about dynamic RAM, though I suppose that may be obvious, in context. Still, it may be helpful to clarify that in your question title. \$\endgroup\$ – jonk Aug 17 '16 at 5:26
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    \$\begingroup\$ Also, the wiki page on dynamic ram answers this reasonably well, including the changes from the old memories I remember. My first experience was in diagnosing and fixing the two MITS ALTAIR 8800 4k dynamic ram boards I'd bought, shown in the lower picture here: s100computers.com/Hardware%20Folder/MITS/4K%20Dynamic%20RAM/… \$\endgroup\$ – jonk Aug 17 '16 at 5:34
  • \$\begingroup\$ What made you think you have to refresh half of your RAM at a time? \$\endgroup\$ – Dmitry Grigoryev Aug 17 '16 at 8:38
  • \$\begingroup\$ @DmitryGrigoryev I thought every cell of DRAM needs to be refreshed periodically \$\endgroup\$ – user119778 Aug 17 '16 at 9:09
  • \$\begingroup\$ @user334283 So the memory controller needs to store one cell while refreshing it, right? \$\endgroup\$ – Dmitry Grigoryev Aug 17 '16 at 9:16

Simplifying a little bit, think of DRAM as being a 2D array of memory cells1. Each cell in the array is a minuscule capacitor.

Along one edge of that array, we have a set of sense amps. There's one sense amp for each cell along that dimension. For either a refresh cycle or a normal read, we activate an entire row (or column, if you prefer to look at it the other direction). When we do that, we read the charge from that row (column) of capacitors into the sense amps. In doing that, we've drained (at least most of) the charge out of the capacitors that make up the memory cells themselves.

That will typically give somewhere in the range of a few hundred to a few thousand bits of data that are sitting in the sense amps. We can then read some of that data out of the sense amps to do to the outside world (if this was a read cycle) or we can just write it back to the memory cells (if it was a write cycle). Or, in the case of a refresh cycle, we read the data from the cells into the sense amps, then turn around and write it back out from the sense amps to the cells.

If the array were square, this would mean the amount of auxiliary storage needed (i.e., the number of sense amps) would be approximately the square root of the total number of bits. In reality, however, the array doesn't have to be square--we can choose a number that's convenient, and set the size in the other dimension to give the total amount of storage desired.

The number of sense amps does have some ramifications with regard to speed though. In particular, it's relatively slow to read data from the capacitors into the sense amps, and much faster to read from the sense amps to the outside world. This is what leads to the typical speed profile for DRAM sticks and such. Most will have a burst length of (say) 8, with a transfer profile that looks something like 17-1-1-1-1-1-1-1. That is, the first word will be transferred 17 cycles after the DRAM receives the (last element of) the address, then another word will be transferred each subsequent clock until the entire burst of 8 is completed.

The number in that initial position varies widely depending on the vintage of DRAM you're talking about. The reality is that the transfer from the capacitors to the sense amps has remained fairly close to constant for quite a long time. As clock speeds have risen, the number of clocks has risen with it to allow for the total time necessary for that transfer.

So, that first (long) transfer time is basically telling us the amount of time needed to transfer the data from the capacitor array into the sense amps. The subsequent transfers are reading data from the sense amps and sending them to the external bus. Of course, in the case of a refresh cycle the data is never written to the external bus. It's just read from the capacitors into the sense amps, then written back from the sense amps into the capacitors2.

That being the case, in a typical commodity DRAM, maximizing speed means ensuring that there are at least as many sense amps as there are bits in a burst. If we're dealing with 64-bit words and 8-word bursts, we want (at least) 64x8 = 512 bits of sense amps. Having more sense amps than that isn't necessarily going to gain a whole lot of speed.

So that argues in favor of the DRAM array being arranged as an Nx512 bit array, with the sense amps along the 512-bit side. A read (or refresh) then consists of activating one of those 512-bit rows/columns in the array, transferring that data to the sense amps, transferring the result out the external bus (if it's a read) and writing the data back to the capacitors.

For current large memory systems, things are a little more complex than that. Rather than a single array of N x 512 bits, the memory is further broken up into banks. For example, a 1 gigabyte DRAM might consist of, say, 8 banks of 1/8th gigabyte apiece (offhand, I don't remember the standard size for a DDR3 or DDR4 bank, but that's at least in the general ballpark).

  1. In reality, in a modern system, there are typically (what could at least be thought of as) more dimensions than that, but 2D is enough to explain the basic idea.

  2. Sense amps are analog amplifiers. They're typically differential amplifiers. In a typical case, the DRAM will contain some dummy cells. To start a read cycle, you pre-charge those dummy cells to (approximately) half the voltage initially stored in a normal cell (or sometimes, to the full voltage, but the dummy cells have half the capacitance). You then read in the charge from the dummy cell and the normal cell, and amplify the difference between the two, so if the cell contained less than the dummy cell, the result will be driven (close) to 0, and if it's greater than the dummy cell, it'll be driven (close) to Vcc. That (now digital) value is then stored into a flip-flop, latch, etc. The dummy cells are used (instead of, for example, just feeding Vcc/2 directly to one of the inputs of the sense amp) to semi-automatically compensate for things like losses in the bit lines, which can vary both across a chip and with the current operating conditions.

  • \$\begingroup\$ Very thorough answer. +1. It might be more helpful to replace " they're roughly like an op-amp with little or no negative feedback" with something like "they are analogue comparators"? \$\endgroup\$ – gbulmer Aug 17 '16 at 22:15
  • \$\begingroup\$ @gbulmer: I've gone into more detail about how the sense amps work. \$\endgroup\$ – Jerry Coffin Aug 17 '16 at 23:02
  • \$\begingroup\$ Lovely answer! I was just trying to simplify :-) \$\endgroup\$ – gbulmer Aug 18 '16 at 0:33

As dynamic RAM chips themselves are designed to be refreshable, they just need to be told (with a special combination of access strobes) which row to refresh. Each chip then reads the 'not too degraded' bit value from all cells in that row simultaneously into internal temporary storage, and re-writes them with fresh topped-up values.

Each refresh cycle, the memory controller cycles through all columns of the RAM. All columns are refreshed, regardless of whether the RAM is thought to contain current data or garbage. The refresh controller 'steals' a cycle periodically to refresh the memory, a column at a time. Typically, RAMs require every row to be refreshed at least once in 64mS.

  • \$\begingroup\$ Exactly, that internal storage you have mentioned. That is my doubt. What and where is that internal storage. If DRAM is of 4GB then don't you think that "internal storage" should be at least half the size of DRAM to temporarily store data of RAM during refresh cycles? \$\endgroup\$ – user119778 Aug 17 '16 at 5:43
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    \$\begingroup\$ @user334283 no, it only needs to be the size of the single row being refreshed. Do you knoiw what a row is, and how rows/coulmns combine to address RAM? Don't forget a 4G memory is made from many RAM chips. \$\endgroup\$ – Neil_UK Aug 17 '16 at 6:00
  • \$\begingroup\$ Once I read that sense amplifiers are arranged as row and one amplifier operates one column so I think it needs to be the size of single column being refreshed and not single row. I obviously know about row and columns. They are like matrix. Each address stores the row and column number and their inter-section gives the location of cell on which data has to be read and written. \$\endgroup\$ – user119778 Aug 17 '16 at 6:10
  • \$\begingroup\$ I corrected, you're right, operations are row specific and not columns. i.stack.imgur.com/JV7SR.jpg \$\endgroup\$ – user119778 Aug 17 '16 at 6:57

The data is read from a row at a time from the memory matrix, destructively via sense amplifier.

Internal (to the RAM chip) circuitry stores the data, for one row only, until it is immediately re-written.

An internal column counter keeps track of which row is next to be refreshed. Every couple hundred microseconds another row is refreshed such that all rows get refreshed within the maximum allotted time time (tens of milliseconds). That time is taken or (better) done in parallel with useful accesses to the memory.

  • \$\begingroup\$ Don't entire memory cells are refreshed simultaneously because refreshing each column and then jumping to next column will increase latency and refresh time. \$\endgroup\$ – user119778 Aug 17 '16 at 5:49
  • \$\begingroup\$ No, one row at a time. The total performance hit due to refresh is still negligible. \$\endgroup\$ – Spehro Pefhany Aug 17 '16 at 6:46

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