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I am designing a circuit and PCB for driving 7 DACs from an FPGA. (DAC is AD9762)

Would it be possible to drive the clock inputs on all 7 DACs with a single clock output (from a PLL output pin) of the FPGA? Or is that a recipe for disaster?

It will be a single ended clock with a max. freq. of 125 MHz.

Or should I use a clock buffer to buffer the clock before each DAC clock input?

If so, is this a good clock buffer? (NB3N551)

Is there a better one I can use?

Edit: Sorry, I should have mentioned: All the DACs will be on a 5"x5" PCB connected through a short (few inches) ribbon cable to the FPGA board.

Edit2: If I can rephrase the question: If I can afford the room and cost of the clock buffers, are there any potential negatives? Or would that be the safe way to do this?

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    \$\begingroup\$ I'm not familiar with these particular chips, but the first thing I would do is ("Circuit design 101") consult the manufacturer's data sheet. What can the clock drive and what do the DACs require, for starters... After I learned what I could from that, if I still had questions I might ask them on an Internet forum... \$\endgroup\$ – UnconditionallyReinstateMonica Jan 19 '12 at 2:32
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    \$\begingroup\$ Important questions to answer this: Can your FPGA supply ~25 mA from its output pin? Can you place the DACs close (within a couple of inches) to the FPGA or do you have some other reasons that mean you have to place them far away? Do you need all of the DACs to update simultaneously (within 1 ns of each other) or is it okay if they update at slightly different times? \$\endgroup\$ – The Photon Jan 19 '12 at 3:32
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    \$\begingroup\$ @mickeyf, we are an internet forum... Jeep, do you have issues with jitter between the DAC outputs? \$\endgroup\$ – Kortuk Jan 19 '12 at 5:28
  • \$\begingroup\$ @mickeyf, the datasheet is actually sparse on clock input circuitry information. I have also started a tech support with this question. \$\endgroup\$ – jeep9911 Jan 19 '12 at 14:12
  • \$\begingroup\$ @ThePhoton, Good points. I think the FPGA can supply up to 24mA. I should have also mentioned that the DACs will be placed on one half of a 5"x5" PCB, but connected to the FPGA through a short (few inches) ribbon cable. Updating the DACs as simultaneous as possible is desirable since this is for a communications application. Is the ~25mA estimate for one DAC or for all 7 DACs? \$\endgroup\$ – jeep9911 Jan 19 '12 at 14:15
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There won't be any problem (except for added power and cost) if you use a clock fanout buffer in this design, but I doubt if you actually need it.

Because your DACs are all located within 5 inches of each other you should be okay with a single receive buffer at the end of the ribbon cable. The fan-out from the receive buffer can be either a star with source-series termination for each fanning out line, as in apalopohapa's answer, or a daisy-chain with a split termination at the far end. The split termination would be a resitor to ground and one to Vcc, providing a Thevenin equivalent of R0 to VCC/2. R0 would match your nominal transmission line impedance, depending on your track geometry. Using a 50 Ohm characteristic impedance is common, but you will save power if you use a higher value like 75 or 100 Ohms.

With a maximum 5 inches between DACs you'd be talking about up to 1 ns difference in the update times between the DACs, out of a sampling period of 8 ns. The time difference would be very repeatable over time and temperature because it just depends on the track lengths between the chips.

N.B. Remember that however you buffer your clock signal, you'll also want to buffer your data signals to manage their delay to maintain correct sample & hold times at the DAC inputs.

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  • \$\begingroup\$ Thanks. It is hard to find a single-ended clock fanout buffer. Ideally I'd like to find one that is 1:8, but I haven't yet. I will probably go with star fanout with series termination. For my data signals, I am using a 74VHC595 Shift Register, so that takes care of the buffering, but I'll probably add series 50 ohm at the output of that as well. \$\endgroup\$ – jeep9911 Jan 19 '12 at 18:52
  • \$\begingroup\$ You can always use "zero delay" clock buffers. Cypress was a good source for 1:4 and 1:8 buffers; I've used their 1:4 single-ended ones for 25MHz MII interfaces before. \$\endgroup\$ – akohlsmith Jan 20 '12 at 1:14
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You can place an R ohm resistor (replace R with the characteristic impedance of your trace) in series for each clock fan out, "as close as possible" to the the pin in the fpga (and don't use internal series resistor that some fpgas offer). This way reflections from every node will die upon coming back to the source, and not cause double triggers at the other inputs.

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    \$\begingroup\$ I would worry that the DACS would have more then a 0 ohm input impedance to a signal that is probably in the mid or high MHz for its spectral content. \$\endgroup\$ – Kortuk Jan 19 '12 at 5:30
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    \$\begingroup\$ For a TTL/CMOS source with daisy-chain routing, termination to ground is not a great idea. Your clock source would need to supply roughly 50 mA in the high state. It's probably preferable to use a split termination (resistor divider) giving a Thevenin equivalent of 50 (or 60 or 70 depending on trace geometry) to VCC/2. \$\endgroup\$ – The Photon Jan 19 '12 at 6:04
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    \$\begingroup\$ Agreed. I removed the daisy chaining alternative from the answer. \$\endgroup\$ – apalopohapa Jan 19 '12 at 10:25
  • \$\begingroup\$ Good idea. Thanks. I was looking at the eval board schematic for the DAC chip and looks like they have a series resistor and a resistor to ground on all digital inputs and the clock. I hadn't thought about adding that, but this is a good idea.<br/> Unfortunately they do not provide values since the lines goes to a header on that board. I can mess with values later, but is a there way to calculate a good approximate? Given DACs are within 5 inches and cables is about the same length. \$\endgroup\$ – jeep9911 Jan 19 '12 at 14:29

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