I am designing a circuit and PCB for driving 7 DACs from an FPGA. (DAC is AD9762)
Would it be possible to drive the clock inputs on all 7 DACs with a single clock output (from a PLL output pin) of the FPGA? Or is that a recipe for disaster?
It will be a single ended clock with a max. freq. of 125 MHz.
Or should I use a clock buffer to buffer the clock before each DAC clock input?
If so, is this a good clock buffer? (NB3N551)
Is there a better one I can use?
Edit: Sorry, I should have mentioned: All the DACs will be on a 5"x5" PCB connected through a short (few inches) ribbon cable to the FPGA board.
Edit2: If I can rephrase the question: If I can afford the room and cost of the clock buffers, are there any potential negatives? Or would that be the safe way to do this?