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enter image description here

Could anybody please help in understading the digital waveforms which are combine with clock and data ?

In the above Picture SCL is normal clock waveform, this can easily readable like High time, Low time.

But here in SDA its like two signals waves merged together seems !! So, Please any one expalin this

Note: this one I2c Waveform

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    \$\begingroup\$ I think you mean SDA not SDL. \$\endgroup\$ Aug 18, 2016 at 16:03
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    \$\begingroup\$ It's not too waveforms superimposed - it is telling you that data may be 1 or 0. Note the ACK bit is always 0 and ditto the start bit. It's this way because it is deemed to be representative of reality. \$\endgroup\$
    – Andy aka
    Aug 18, 2016 at 17:41

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The individual bits can be either high or low, depending on what device you are addressing, whether you want to read or write and the actual data that is read/written.

EDIT: Let's first consider the transition between the start condition and the A6 bit. You can clearly see, that on start condition SDA must be low, but then, depending on the actual address, it can go either low or high.

Between A6 and A5 you have two lines crossing: one going low to high, another one -- high to low. Strange enough, it doesn't necessarily mean that the signal has to change. In fact, it can either stay low, stay high, change from low to high or the other way round.

After R/W, again, SDA should go low (or stay low, if R/W was 0), regardless of the data you are transmitting and the address. In case it was high, it would indicate that there's no slave with given address or that an error occured.

2nd EDIT: Think of these address and data bits as qubits: in the world of datasheets, they can be either low or high, it doesn't really matter. But if you were observing a waveform captured by a logic analyzer, you would see that they have defined state.

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Any position in the digital waveforms where there is only one value indicates that only one value is acceptable/expected, e.g. at the beginning and end of the stream SCL and SDA must be high, and the ACK bits should be low if the request was successful.

The reason for the 'merged' waveform is to demonstrate the relative transition timings. The address bits and data bits can be either one or zero, but how do you show this on a waveform? A blank area is not particularly helpful and a mid-level voltage is just wrong, so to show how the timing of the SDA line must be synced to the clock signal on the SCL line, an either-value-works-here 'merged' waveform is used to show what the timing looks like without implying only one value is acceptable.

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