I have built the standard CMOS inverter in reversed configuration by putting NMOS on pull up side and PMOS on pull down side. This will work like a buffer but the the upper and lower bound of the output will not be the Vdd and Gnd. Instead, as NMOS passes weak '1', the upper bound will be Vdd-Vth. The PMOS passes weak '0', the lower bound of output will be Vth of PMOS.
But the question is, what happens if the PMOS leakage increases. Will it affect the lower bound of the output, bringing it below than the Vth of PMOS?