# Effect of increased leakage of PMOS in reversed inverter configuration

I have built the standard CMOS inverter in reversed configuration by putting NMOS on pull up side and PMOS on pull down side. This will work like a buffer but the the upper and lower bound of the output will not be the Vdd and Gnd. Instead, as NMOS passes weak '1', the upper bound will be Vdd-Vth. The PMOS passes weak '0', the lower bound of output will be Vth of PMOS.

But the question is, what happens if the PMOS leakage increases. Will it affect the lower bound of the output, bringing it below than the Vth of PMOS?

• In your circuit the PMOS FET's Source and Drain are reversed, so it will never turn on. However its body diode will start to conduct when the output voltage gets above ~0.5V. – Bruce Abbott Aug 19 '16 at 2:54

• assuming $\kappa=0.7$, you see about 1 decade of current per 100mV. That means that a 200mV change in the gate will give you 100x change in current. The majority of the work it do is subthreshold digital. If you want to look for near threshold or subthreshold work, you should look at the papers from the S3S conference (s3sconference.org). – b degnan Aug 19 '16 at 16:56