4
\$\begingroup\$

I am trying to learn how to implement negative feedback to a common-emitter configuration.The goal is to reduce distortion by sacrificing some of the gain.

schematic

simulate this circuit – Schematic created using CircuitLab

This is how the complete circuit should look.

I am talking about \$R_{NFB}\$ (I have not inserted it yet).This site specifies that after having everything calculated(excluding \$R_{NFB}\$ and \$C_4\$),its value should be calculated in order to preserve the initial gain.The formula to be used for this gain is now \$\frac{R_L}{R_{NFB}}=GAIN\$ at high frequencies.After getting its value,\$R_E\$ must be recalculated so \$R_E\$+\$R_{NFB}\$ is the same as the \$R_E\$ original value.

In other words,I understand that I am supposed to unplug \$R_E\$ and put it in series with \$C_3\$ and call it \$R_{NFB}\$.This doesn't make sense to me.I know that this negative feedback works by allowing a certain part of the AC output signal on the emitter,reducing the shunt effect of the bypass capacitor,but I don't understand the calculations.

How am I supposed to calculate the value of \$R_{NFB}\$?

\$\endgroup\$
  • 1
    \$\begingroup\$ Isn't C1 slightly misplaced? (And no, you don't unplug Re.) \$\endgroup\$ – jonk Aug 20 '16 at 8:41
  • \$\begingroup\$ @jonk It was,I edited the post.By unplugging Re I mean connecting it in series with C3 and tying the emitter to the ground without anything else between. \$\endgroup\$ – Daniel Tork Aug 20 '16 at 9:01
  • \$\begingroup\$ And that doesn't make much sense to me. Well, it does, but not in this case. Emitter to ground makes for a very temperature dependent design and you absolutely need global negative feedback (not at the emitter) to linearize things when you do that. \$\endgroup\$ – jonk Aug 20 '16 at 9:59
6
\$\begingroup\$

It's late here, so I will write a little but will have to add more after I get back up in the AM....

Usually, you know what your \$V_{cc}\$ is. And you know what you want to use as the quiescent collector current, \$I_q\$. I don't agree with your web pages about setting the DC point for \$Q_1\$'s collector, though. Instead, I generally want the DC point for the emitter to be at least \$1V\$ above ground, to aid temperature stability due to the emitter's little-re (\$\frac{k\cdot T}{q\cdot I_C}\$) dependence on T. More is better. But I shoot for \$V_e \ge 1V\$ as \$V_{CC}\$ allows. I also know that to stay well out of saturation, I want \$V_{ce} \ge 2V\$ at all times. So I've already eaten up \$3V\$ of headroom, before I've started. So I take \$V_{c_{q}} = \frac{V_{cc} + 1V + 2V}{2}\$ as the quiescent voltage for the collector. For example, if \$V_{cc} = 10V\$, then \$V_{c_q} = 6.5V\$; not \$5V\$ as your lessons would seem to have you do. This provides \$\pm 3.5V\$ collector swing. \$5V\$ is just too low and squeezes the BJT too tight and leaves nothing for temperature stability. It works fine if you have lots of headroom. But with low headroom, everything starts to matter.

From \$I_{c_q}\$ I can estimate \$V_{{be}_q}\$ and from that I can estimate the operating point for \$V_{b_q}\$, knowing that I've set \$V_{e_q} = 1V\$. Also, of course, it's easy to calculate \$R_c\$ and \$R_e\$, too. And I can also estimate \$I_{b_q}\$ and from that I can figure out the divider needed for the base. This is all discussed on your DC Conditions page.

So let's do a full-up DC design to start, using \$V_{cc} = 10V\$ and \$I_{c_q} = 2.5mA\$:

schematic

simulate this circuit – Schematic created using CircuitLab

I hope you can figure out where the values came from, given that you accept where I set the voltages and picked out the quiescent collector current.

The reason, again, for \$R_e\$ is because there is, in effect, a tiny, temperature dependent thermal voltage at the tip of the BJT emitter. If you take into account \$I_c\$, then this is converted into a tiny, temperature dependent resistor value often just called 'little-re'. Regardless, you want to overwhelm the thermal variations there with something. Since the value of \$\frac{k\cdot T}{q}\$ is on the order of \$26mV\$, jacking the emitter up to about \$1V\$ makes the thermal voltage tiny by comparison, so when it varies a bit over temperature it doesn't affect the emitter's operating point very much. So that's why it's there.

Ah. You thought perhaps that it was there because of the DC gain I might have wanted? No. It's there to set the DC operating point for thermal stability. Of course, yes. The gain here is terrible. It's \$\frac{1400}{400} \approx 3.5\$. And I can't really change it, either, if I want to keep my thermal stability and keep the transistor well out of saturation, etc.

In short, I'm trapped. No wiggle room, at all. That's not so good.

Luckily, AC comes to the rescue. let's say the new schematic looks like this (I'm still leaving out C4. For these purposes, it's just not necessary and I'll let you worry about it on your own):

schematic

simulate this circuit

The input is AC. The emitter of \$Q_1\$ will follow that input with slightly less than a gain of \$1\$. If \$C_2\$ is large enough in value, then it will essentially be a short circuit (or wire) and won't impact the impedance of the \$R_{ac}\$ leg. So, at AC, you can see that the effective AC impedance of the entire emitter load is \$R_{ac} \vert\vert R_{dc} \approx 58\Omega\$. Now, the gain is more like \$\frac{1400\Omega}{58\Omega} \approx 24\$. And we get control over the gain at AC. But at DC, the emitter is still sitting high up, at around \$1V\$ where we want it.

So we get to have our cake and eat it, now.

There are two perspectives shown on your web page:

enter image description here

Either works. The difference is that the left side topology allows you to easily set the AC gain-setting resistor more directly, as the capacitor ends up bypassing the other, DC-setting, resistor. However, this forces you to divide out the DC resistance needed to set the emitter voltage, so that becomes a little more complicated. The right side topology makes setting up the DC resistance for a given emitter voltage and quiescent current trivial. But it makes the AC gain resistor's value a little more complex to work out since you have to treat it in parallel to the DC setting resistor. It's just two different ways of approaching the same thing.

There are also some bootstrapping techniques I hope you also learn about. The simplest uses the fact that the emitter follows the input at a gain of about \$1\$ to actively drive the base's resistor divider node and where the signal directly drives the BJT base, with a new resistor now between the divider node and the BJT base. The capacitor develops an equilibrium voltage across it that is just enough to make up for the difference across it. And since one side of that new resistor is driven by the signal itself and the other side is driven by a low impedance emitter that is following the signal pretty well, the new resistor itself sees the same voltage (DC bias plus AC) on both sides, so almost no current flows. And this very much increases the input impedance. Which is nice. And there are other improvements, as well.

Here's an example of a simple bootstrap:

schematic

simulate this circuit

(Take note that I switched over to the other emitter configuration we've discussed here, just to do something different.)

The idea is that the signal directly drives the transistor base through \$C_1\$ and also that signal is on one side of \$R_3\$. \$R_3\$ is a DC path to allow \$C_1\$ to find its equilibrium state voltage and as a DC path for \$Q_1\$'s starting up the required \$V_{be}\$ to put \$Q_1\$ into the active region. \$C_4\$ picks up the low-impedance copy of the signal at the base (so there is some current drive available) and drives that back to the divider node. Now, slight variations in the signal will move \$Q_1\$'s base up and down, and these will be copied across to \$Q_1\$'s emitter, which will then drive those same changes back to the divider node. Assuming that \$C_4\$ has exactly the right voltage across it (given enough time, it will) to exactly match the difference between the quiescent emitter voltage and the quiescent divider node voltage, then all this works fine. The divider node will move up and down, driven by the emitter which is copying the base, and the other side of \$R_3\$ will be also moving up and down roughly in phase, as well. So \$R_3\$, if everything were perfect (and it isn't), would have the exact same voltage across it and would then have no current flowing in it, at all. The reality is that the emitter does have a copy, but at a gain slightly less than \$1\$. And capacitors, even largish ones, will add a slight phase difference. Etc. But it works pretty good just the same. And it greatly reduces the load on the signal source.

And in any case that is only the beginning. Practical amplifier stages can and will take into account a lot more than all this.

\$\endgroup\$
  • \$\begingroup\$ I'll also bear in mind your way of computing component values,thanks :) \$\endgroup\$ – Daniel Tork Aug 20 '16 at 12:08
  • \$\begingroup\$ @Daniel: You have some reasonable answers. You should select the best one for you, unless you are waiting for more to happen. \$\endgroup\$ – jonk Aug 20 '16 at 15:57
  • \$\begingroup\$ Well,you said in the beginning that you had some more to add,but if this is all you want to write,I'll go on. \$\endgroup\$ – Daniel Tork Aug 20 '16 at 19:01
  • \$\begingroup\$ Also,I have a question about the b setup.You said that the feedback resistor's value won't affect the DC conditions,right?Did I understand correctly? \$\endgroup\$ – Daniel Tork Aug 20 '16 at 19:05
  • \$\begingroup\$ @Daniel: In the case of (b), the AC resistor doesn't impact the DC conditions set up by the DC resistor. The DC quiescent current can ONLY flow through the DC resistor. (The capacitor blocks DC currents.) However, in the case of (a), the DC quiescent current flows through both resistors, so it is the series of the two that sets up the DC set point for the emitter here. \$\endgroup\$ – jonk Aug 20 '16 at 19:24
2
\$\begingroup\$

I don't understand the calculations

Voltage gain, in simplified terms, without the extra RNFB and C3 is: -

\$-\dfrac{R_L}{R_E}\$

So, if Re is lowered then gain increases but then the DC operating point is shifted away from half way between the rails (optimized for maximum undistorted output swing).

After getting its value,RE must be recalculated so RE+RNFB is the same as the RE original value

Only if series connected feedback (picture A below) is used as per the diagram in the link you have: -

Your circuit uses parallel components (B) so this recalculation is invalid.

enter image description here

So, RNFB is used to reduce Re and, by putting RNFB in series with capacitor C3, the DC operating conditions are unaffected.

How am I supposed to calculate the value of RNFB?

If you know what voltage gain you want then use the formula to derive a theoretical value of emitter impedance and this emitter impedance is Re||RNFB. Clearly, because RNFB is in series with C3, at DC the gain is \$-\dfrac{R_L}{R_E}\$.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.