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I was reading about Benefits of High Switching Frequency, I found the following:

  1. Smaller converter can be cheaper – up to a certain power output. Beyond that power level small size might be worth some added cost.

  2. Transient response can improve with higher switching frequency.

Drawbacks of High Switching Frequency:

  1. Efficiency is worse, Switching loss is proportional to switching frequency.
  2. Dropout voltage (minimum VIN) is higher.

The source : http://www.onsemi.com/pub_link/Collateral/TND388-D.PDF

Can you describe to me those Benefits and Drawbacks ?

Thanks

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  • \$\begingroup\$ Could you be more specific? If I were asked to describe the benefits and drawbacks, your question would be approximately my answer. \$\endgroup\$ – WhatRoughBeast Aug 21 '16 at 12:45
  • \$\begingroup\$ I do not understand the Drawbacks and Benefits which I wrote. Can you describe them for me? thanks \$\endgroup\$ – Joe Aug 21 '16 at 12:47
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    \$\begingroup\$ Something not yet addressed that I'll mention: EMI compliance. Higher frequencies can radiate more easily, requiring that the designer pay better attention to the power supply design. However, that is not a point your were asking to have addressed. \$\endgroup\$ – user2943160 Aug 21 '16 at 14:23
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Smaller converter Smaller can be cheaper – up to a certain power output Beyond that power level small size might be worth some added cost.

The basic deal is that the size of the magnetic circuit reduces as the frequency increases as it gets "recharged" more often so it doesn't need to be as big. Obviously there will be a trade-off between cost of material and cost of miniaturisation and there will be a point at which the sum of both is a minimum. This is what the designer will aim for.

Transient response can improve with higher switching frequency.

A transient load will cause the voltage to dip. High frequency switching allows rapid correction as the interval between pulses is shorter.

Efficiency is worse: Switching loss is proportional to switching frequency.

The reason SMPS is efficient is that the switcher is either fully off (no current so VI is zero) or fully on (high current but low voltage so VI is still low). In contrast a linear voltage regulator will be partially on, acting as a resistor and wasting power as heat.

The problem is that in going from off to on or vice-verse there is a short time that the switcher is in transition and relatively high power is dissipated during the transition. The transition time becomes a higher percentage of the duty cycle the higher the switching frequency. Therefore the transistor losses become higher too.

This also has to be factored into the design mix to find the best balance between cost and performance.

Dropout voltage (minimum VIN) is higher.

I can't help you with this at the moment.

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  • \$\begingroup\$ Joe, please un-accept my answer for a day or so to encourage other answers. You'll get a variety of viewpoints which should improve your overall understanding. Then pick the best to accept. Thanks anyway! \$\endgroup\$ – Transistor Aug 21 '16 at 13:44
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I will hit the main points here (people spend careers in this).

Consider a typical buck converter:

Buck converter annotated

The switching frequency affects a number of things in the selection of the components:

The output inductor is chosen according to this equation (for this current mode converter):

\$L\ = \ \frac {1} {(f) (\Delta I_L)} \cdot V_{out} \left (1\ -\ \frac{V_{out}}{V{in}}\right)\$

Clearly, the higher the switching frequency, the lower the inductance which (for a given family of inductors) means fewer windings for less resistance, leading to lower core losses for a given amount of ripple current (the \$\Delta \ I_L \$ term above).

With a higher switching frequency, the loop crossover frequency can be higher, resulting in faster response as the loop has gain at higher frequencies than otherwise attainable; this also simplifies ripple current suppression as smaller capacitors are required for a given maximum ripple current.

The loop crossover frequency has to be chosen such that switching noise of the main and synchronous switches do not interfere with loop response and compensation; a typical value is between \$\frac {F_{sw}} {4} \ to \ \frac {F_{sw}} {10} \$. The higher the switching frequency, the higher the crossover frequency can be.

The downside is that the losses in the switches are proportional to frequency.

The main switch has losses that are proportional to:

\$ P_{main}\ \alpha \ \frac {V_{out}} {V_{in}}\ \left ({I_{out(max)}} \right)^2 \ \left (1\ + \delta \right) R_{ds(on)} \ + {V_{in}}^2 \ \left (\frac {I_{o(max)}} {2} \right ) \ F_{sw}\ R_{DR}\ \cdot \left (C_{miller} \right ) \$ where \$ \delta \$ is a thermal dependency of \$R_{ds(on)} \$ and \$R_{DR}\$ is the effective driver resistance.

\$F_{sw}\$ is the switching frequency of the converter.

I have ignored the sub-threshold losses for now; what should be clear that as the switching frequency increases, so do the capacitive losses in this switch and they will often exceed the core losses associated with a larger inductor for lower frequency operation.

The Synchronous switch has losses of:

\$ \left (\frac {V_{in}\ - V_{out}} { V_{out}} \right ) \left (I_{o(max)} \right ) ^2 \left (1\ + \delta \right) R_{ds(on)}\$ and is therefore fixed for a given duty cycle.

At higher frequencies, the proportion of the time that both switches must remain off (to prevent shoot through) is higher, and that limits the duty cycle.

As the duty cycle of a buck converter is \$ \frac {V_o} {V_{in}} \$ then a reduced duty cycle implies that the \$V_{in}\$ term must increase for a given \$V_o\$ for higher operating frequencies.

The duty cycle for the synchronous switch is \$ \frac {V_{in}\ - {V_{out}}} {V_{in}}\$ and therefore lower main duty cycles increase the loss in this device as \$V_{in}\$ increases.

After that it will come as no surprise to find that the main switch is chosen for minimal \$C_{miller}\$ and the synchronous switch is chosen for minimal \$R_{ds(on)}\$

So different operating frequencies each have their own challenges; start-up is particularly difficult at higher operating frequencies and some converters utilise frequency foldback for times when the duty cycle would otherwise be too high for proper operation.

I have not addressed loop compensation as this is a major subject in its own right.

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I think the other answers are good (and cover most of the points), but here is something that might cover what you mean by drop out voltage.

  1. Power supplies have minimum and maximum on time per a switching cycle
  2. On time or off time limitations change the maximum ratio possible between input and output relative to switching frequency
  3. Due to this, a high frequency may not permit a high step up/down ratio without a transformer (e.g. 50V down to 1V (assuming 95% efficiency here) might be near impossible at 1MHz since it would require (1V / 50V*0.95%) * 1us = 21ns on-time for control (top) FET.

Another concern is sensitive frequency ranges. For example, avoiding 535 to 1605kHz helps to not incidentally generate noise in AM radios.

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