Having one of those moments again where you feel you are missing something seemingly obvious.
In multilayer PCB stacks, you have alternating layers of copper and substrate (either prepreg or core). The question is, does this result in voids?
Obviously the copper has some thickness, so if you pattern the copper, and then attach a layer of dielectric (e.g. FR4, rogers, etc.), then surely the areas where there is no copper would now be voids in the structure. Unless of course the dielectric is a conformal layer or the voids are in some way filled?
As an example. Take a design with a 6-layer stack up and say you want to do impedance controlled traces - is it possible to put a reference place on, say, layer 3, and the signal on layer 1 - assuming of course a gap is left in the copper on layer 2. If there are in fact voids caused by the thickness of copper on layer 2, then this wouldn't be possible because there would be a gap in the dielectric. I'm not planning on doing this, it's just a curiosity.