Actually in soft switching converters an increase in frequency increases switching losses?

Can anyone explain why?

  • \$\begingroup\$ Each switching event has an amount of energy loss \$Q_{LOSS}\$ , with increasing the frequency there are more events. \$\endgroup\$ – Marko Buršič Aug 23 '16 at 17:45
  • \$\begingroup\$ can u explain some elaborate? \$\endgroup\$ – Raj Aug 23 '16 at 17:49
  • \$\begingroup\$ @raj: Can you explain what you didn't understand when you looked it up? \$\endgroup\$ – Transistor Aug 23 '16 at 17:51
  • \$\begingroup\$ consider a mosfet in that for turn on we have to control vgs voltage for switching on and off,but 5V input is equal to 5v output. \$\endgroup\$ – Raj Aug 23 '16 at 18:04
  • \$\begingroup\$ OK, I'm considering it. Now what? This is now sounding like a homework question with no attempt at research. \$\endgroup\$ – Transistor Aug 23 '16 at 19:08

The key to your question is 'soft switching'. So every 'edge' in the output there is a period of time when the output device is partially on- instantaneous power loss will, of course, be the current multiplied by the voltage across the device if we ignore any parasitic reactances.

You can read more about the actual calculation of MOSFET losses here, but the key thing is that the loss is a little package of energy that has to be dissipated that occurs once per edge. The more edges in a second (higher frequency), the more total energy per second (which is power).

From the above AN:

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Every time a switching circuit switches, even when it is unloaded, the stray capacitance at the output node has to be charged or discharged, in order for the output node to change voltage level. Since the switching element is not ideal, i.e. it has some resistance, the current needed to charge/discharge must flow through that element and this causes losses.

Since losses happen only when the switch changes states (assuming zero losses when the switch is completely on or off), more switch events per second means more losses per second, i.e. an increase of power loss.

I assumed zero loss during static operation (no switching), because if the switching element is good enough it has either zero current flowing through it or zero voltage across it when it is not switching, so zero static power loss (ideally). The case is different when the switch is in the process of switching: in this case both current and voltage are non-zero, hence their product is the power lost in the switch.

Assume, just for example, that an unloaded switch must charge a stray capacitance of 100pF at 5V. This means that at the end of the switching action, after \$\Delta t\$ seconds, the capacitance has been charged with a charge \$Q=C\cdot V=100pF \cdot 5V = 500pC\$. Let's assume, for simplicity, that the switch has an \$R=100m\Omega\$; resistance. Since on average \$Q=I\cdot \Delta t\$, then the power loss in the switch is, on average (I say on average because here Q and I are related by an integral in the general case):

$$ P=R\cdot I^2=R\cdot\left( \frac{Q}{\Delta t} \right)^2 = R \cdot \frac{Q^2}{(\Delta t) ^2} $$

From this last equation you can see that the switching loss average power is inversely proportional to the square of the switching time, i.e. the losses are indeed proportional to the square of the switching frequency.

(Choose different values of \$\Delta t\$ and plug-in the values if you need actual numbers to convince yourself).


The simple answer is that a certain amount of energy (E) is dissipated each time a transistor switches. Each time you switch, you dissipate that same amount of energy. If you siwtch at some rate (F) Hz, then you will dissipate that energy F times per second. Therefore the dissipated wattage (W) due to switching losses is ....

W = F * E

The energy E consists of many parts.

1) Capacitive losses due to Cds, Cdg, Cgd.

E1 = 1/2 Cds * Vds^2 + 1/2 Cdg * Vdg^2 + 1/2 Cgd * Vgd^2

2) Increased conduction losses during the turn on/off times.

That dissipated energy is proportional to the load current, the supply voltage, and the switching time.

E2 is proportional to V_ds * I_load * T_off

3) Body diode conduction losses during "dead-time" in half bridge configurations.

E3 is proportional to the dead-time and I_load


Dynamic losses are the main losses in logic unless they are "asleep" with just static leakage current. The same occurs in switching converters except they also have real load currents in the power transfer.

Each switch has an ESR or RdsOn which dissipates power from each current pulse driving the input capacitance of the CMOS load only during the transition Ic~Cdv/dt

Therefore the power dissipation increases with each pulse and is proportional to frequency depending on number of average gates making this transition.

Smaller lithographic reduces the load capacitance and power while a reduction in RdsOn With low voltage CMOS from ~50 to ~25 Ohms also reduces the dynamic losses.

The soft switching effect in converters is to reduce the dv/dt peak currents.

WHen load capacitance is significant raising the switching frequency results in more dynamic losses, just as in logic to the point where it is less efficient. While raising the frequency allows smaller choke inductance to be used ,which is beneficial at higher load currents.

It should also be noted that in a common switch family with different RdsOn values, Ciss*RdsOn product is a constant with the same topology and FET design and comparing vendors, voltage limits and this product may lead to better performance with lower values. We call this a Figure of Merit (FoM) in making MOSFET switch selection among other choices.


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