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The schematic of a SR flip-flop is the following:

enter image description here

The equation for the output is:

$$Q^{t+dt}=(S+\bar{R}Q)^{t}$$

What I don't understand is that as the output \$Q\$ is given again as an input and the same happens with the \$\bar{Q}\$, doesn't this create a race condition?

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  • \$\begingroup\$ That's a SR latch with an enable pin... \$\endgroup\$ – Bradman175 Aug 24 '16 at 0:00
  • \$\begingroup\$ @Bradman175 My book uses the two terms interchangeably. \$\endgroup\$ – Adam Aug 24 '16 at 0:02
  • \$\begingroup\$ Well the actual definition between latch and flip-flop is pretty vague so you're not wrong. I'm just saying that this has slightly different capabilities compared to a true edge triggered flip flop. \$\endgroup\$ – Bradman175 Aug 24 '16 at 0:09
  • \$\begingroup\$ @Bradman175 I know and you are right but the question is pure theoretical and I don't talk about an actual electronic part. \$\endgroup\$ – Adam Aug 24 '16 at 0:11
  • \$\begingroup\$ Anyways trying to figure out the race condition. Gotta to do with timing. \$\endgroup\$ – Bradman175 Aug 24 '16 at 0:11
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On startup, there is a race condition between between Q and Q' settling. Also, if both S and R are simultaneously toggled active, there is a race condition and invalid state. However, in normal operation, a race condition is pretty rare.

The case in which there could be a race condition during normal operation (only S or R is active at a time) is when the S or R active edge is not held long enough (minimum pulse width is violated) for the outputs Q and Q' to properly settle. In this case, there will be a race between the Q/Q' which is propagating through the feedback loop to stabilize the system, and the inactive edge of S or R (whichever caused the toggle).

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This question has been answered here!

There is indded a race condition in the begining. Once in initial stable state is reached then there is no race condition anymore.

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