I'm very new to digital design (my background is software). I'm trying to make use of some block RAM on a Xilinx FPGA, and I want to know what the usual methods are for setting up the RAM control signals w.r.t. the clock.
I currently have a single clock used by all of my design. The RAM can perform a read/write every rising edge, and I want to use it at that rate. Of course, the control signals need to be set some time before the rising edge of the clock. I imagine there are a few ways to do this:
- Set the signals on the falling edge of the clock.
- Set the signals on the rising edge. The synthesis tool is clever enough to know what I want, knows the required setup time, and takes care of everything.
- Set the signals on the rising edge. The synthesis tool isn't clever enough, but I can do funny things with timing constraints to get the signals set up early enough.
- Use two clocks slightly out of phase, set the signals on the rising edge of the leading clock.
- Some other approaches?
Which of these are possible, which are actually good or usually used, and are there any advantages or disadvantages to help choose between them?
Edit: I'm using plain VHDL for reasons of portability, and not using Xilinx-specific CoreGen or primitives. I'm following Xilinx documenation though, and writing the VHDL in such a way as to let the tools infer the correct RAM type ("RAM HDL Coding Guidelines in UG687 if anyone is interested). The tools seem to be doing this correctly.