I'm trying to use an LT8500, which comes in a curious and interesting package: 6x6mm QFN with 0.55mm pitch, a second row and an exposed pad:

LT8500 land pattern

There is 0.25mm of empty space between pads. Can I still route that on a two layer board, or should I switch to four layers and use microvias? Is there an option I've missed?

  • \$\begingroup\$ while 0.08mm track, 0.08mm gap would fit, you may find it greatly restricts your choice of PCB fabricators ... I'd be looking at vias. \$\endgroup\$ – Brian Drummond Aug 24 '16 at 23:50
  • \$\begingroup\$ That also chip comes in an alternate package without the inner rows, according to the datasheet. \$\endgroup\$ – Nick Alexeev Aug 25 '16 at 0:06
  • \$\begingroup\$ @NickAlexeev, that package variant is obsolete, and no longer sold. \$\endgroup\$ – Simon Richter Aug 25 '16 at 0:38

The key point on this footprint is how to fan-out the inner row of pins.

Some physical dimensions:

  • 0.45 clearance between the inner pads and the thermal pad.

  • 0.55mm pitch between pads

  • 0.2mm clearance between pads

Some options:

  • Using a 0.07mm/0.07mm trackwidth/gap (less than 4mils/4mils) to fanout between outer pads. This is a really high requirement for the PCB manufatcurer and it will increase the the PCB cost a lot.

  • Using microvias and via-on-pad technology to fanout the inner pad to a different layer. I think this is the only solution. As well, it will be expensive and it will limit your choice of PCB fabricators.

The number of layers:

I reckon this kind of package is not supposed to use in a 2 layers PCB at all. 2 layers PCB and microvias is not good engineering choice. I think it should be at least 4 layers. You should consider the type of microvias and its aspect ratio.

You might consider to choose a different component with a more "easy-to-use" package.

enter image description here

| improve this answer | |

enter image description hereIf you don’t plan to operate this device at high temperature you can reduce the size of the exposed pad solder footprint to make room for normal through visas to go to a lower layer. Confirm your layout with with the IC manufacturer for production projects but for non-production projects it should be fine.

| improve this answer | |

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.