This question sprung out as a curiosity while I was trying to understand CPUs. But I could not find a good answer on the internet. So, I am asking here: Are the commonly used uC's like PIC 10f200, PIC 12f683, PIC 16f87, the ATmega one's used in Arduino and the STC 8051 microcoded or hardwired?
I am guessing they all are hardwired. But seeing that the PIC execute 1 instruction in 4 cycles, they feel a bit CISCy and have me wondering.
Thanks for all answers.
The PIC, the Atmel and 8051 are hardwired. CISC does NOT mean automatically that a processor has microcode. Moreover, as in many other technologies (FPGA vs CPLD vs processor vs DSP), the boundaries are getting more and more fuzzy, and today it is very difficult to trace the line between CISC and RISC.
We would have to work there of course, and I dont, but it is very likely they are not microcoded. Microcoding is mostly an x86 thing and they even may not be microcoded anymore. The 6502 we now know had a PLA with a table, but something like a PIC is somewhat trivial to implement no need to overcomplicate it
Multiple cycles is not an indication of risc or cisc, even when a processor advertises one clock per instruction that is misleading it takes a handful to several per instruction, they just have a pipe of similar size and some prefetching to TRY to get the average to 1 per, other than superscaler and other terms for multiple execution paths, a single pipe/path strives to be at best one per, but is often slower since the bottleneck is feeding the processor.
Note there are clones of pics and 8051s and others. Give 100 programmers a programming task you are going to get between 1 and 100 different solutions assuming they all complete the task correctly. You wont get exactly one and you wont get exactly 100 but somewhere in between. Take an instruction set and year after year make improvements on your product, or if it is legal then there may be clones and each clone can/will be implemented differently. No reason to expect them to be the same.
I dont remember if it is the lc-3 or some other educational processor that for teaching purposes they generated this massive microcoded mess. You can implement that core in a few dozen lines of verilog or vhdl, no reason to make such a mess other than for teaching purposes. Look at the risc-v right now it is a spec and there are already multiple implementations coming out, and was kind of a goal to define the instruction set and make some tools but ideally make it open so that others can clone it. Will see how it survives in the courts when tested, a number of the corporations jumping in to play hold many of the patents that could pose a threat so maybe they are going to look the other way, or maybe they are diving in to take it over legally.
