USB trace impedance calculations, with termination resistors

Question

I'm designing a PCB featuring a Renesas RZ-A1 microcontroller, and want to check that I'm doing my USB D+ and D- traces correctly.

This application note from Fairchild (alternative link), which is one of the top Google results, says that D+ and D- trace single-ended impedance should be 45 ohms.

Using the EEWeb Microscrip Impedance Calculator, I find that with 1oz/ft^2 copper and a substrate height of 0.08mm, my trace width should be 0.17mm in order to achieve this 45 ohms.

The Fairchild application note also says that the differential characteristic impedance of the D+ and D- lines should be 90 ohms.

Using the EEWeb Edge Coupled Microstrip Impedance Calculator, I find that the spacing between my traces should be 0.098mm in order to achieve this.

Does that look right?

Next part of the question - I understand that series termination resistors are needed on D+ and D-. The Renesas RZ-A1 recommends 22 ohm ones. Does the presence of these resistors change anything in terms of the calculations above? E.g., because the resistors are already providing 22 ohms, should I in fact be aiming for 23 ohm single-ended impedance rather than 45, or something like that?

Answer 1

question 1: This doesn't seem right

The default Er is 4, but usually the ER for standard FR4 is around 4.6. Although for this calculation you will need the effective Er because the top of the trace is not embedded in FR4.

with Er=4.6, conductor with=0.17mm and dielectric height of 0.08mm the effective Er is 3.2215. but the EEWeb Edge Coupled Microstrip Impedance Calculator not giving me the same values as the polar si800 field solver or the free Saturn PCB toolkit.

use the Saturn PCB toolkit it is free and it alco can compensate for the plating trapezoid shape of the traces and other production process variables.

question 2: The trace impedance should be as close as possible to the caracteristic impedance of the cable, the connector and the termination on the receiver end. Any impedance discontinuities will cause reflections and cause degradation to the signal. So keep the trace differential impedance asc lose as possible to 90ohms the single ended impedance is important but not so important because in the cable the signals are transported in a differential pair. the series termination resistors are used for 4 main reasons.

1. To reduce EMI this is if the product is going to be EC approved.
2. To absorb near end reflections like the ones caused by the connector.
3. To control/reduce the signal level in the receiver end because there are maximum drive voltage limits in the HS-USB compliance test.
4. To crudely improve ESD protection (when the system needs better ESD protection a proper low capacitance clamping device should be used instead)

The only undesired effect is increased slew-rate, but the manufacturer recommendation usually takes this into account.

As a example of using the series resistors to improve compliance please see the following picture. Although the eye diagram perfect, the teat packet failed because it went over the boundaries as signaled by the 3 red dots in the bottom right of the template boundary box. this is because there is some overshooting. The series resistors can be used in this case to reduce the overshooting.

the test passes after increasing the series resistor value by 10 ohms.

Guidelines:

• Keep the series termination resistors as close as possible to the pads of the driving device for better absorption of the near end reflections.
• Avoid running the running the differential pair over a ground plane discontinuity.
• Keep the differential pair away from any vias, pads or copper in the same layer at least 3 times the inter-pair skew or the dielectric height whichever is the largest.
• simulate everything
• if you can reuse a design that is already passing compliance, just do it don't reinvent the wheel.

Answer 2

If you follow the Mfg's specs and app notes you will get the best signal integrity. Since the FET inside these class of chips has low RdsOn (10 Ohms) but a wider than desirable tolerance ,a series R must be added but trace impedance should still be 45 Ohms +-10%

Note that the app note uses 42 Ohm at room temp for driver output impedance incl. 29 Ohm.ext. This gives their optimum eye pattern for margin.

Note also that if you scale dielectric thickness up then , so you can uses larger gaps and tracks. **2:1 ratio for track width:FR4 thickness is about right. **

This is because characteristic impedance is due to a fixed ratio if inductance/capacitance ratio or track width to board thickness ratio. The same is true for coax diameter of signal/ground ratio. Distributed Inductance related to aspect ratio of the signal path and capacitance is controlled by the conductor gaps.