0
\$\begingroup\$

I am using Xilinx ISE v8.1, and VHDL language. I have a simple design implemented using behavioral approach, which gives me a set of combinatorial functions.

I can see the schematic of the outcome after synthesis by going to "Synthesize - XST" - "View RTL schematic". But what I am looking for is the Boolean algebra equations. Do we have an option in there to extract the equations? That will help me to feed the equations into another tool and do some other processes on them.

I just can not find the option that shows the generated function equations.

\$\endgroup\$
7
  • 1
    \$\begingroup\$ They will be present in some form the generated VHDL netlist (via some option like "generate VHDL netlist for post-synthesis simulation"). But it won't be pretty, probably structural VHDL interconnecting AND gates. Don't think I've ever seen a way to get the actual boolean equations. (Also, schematic viewer was buggy as hell around ISE8, consider upgrading to 14.7 for this work) \$\endgroup\$
    – user16324
    Commented Aug 25, 2016 at 9:31
  • \$\begingroup\$ was about to say.. ISE8 ?? Are you sure? \$\endgroup\$ Commented Aug 25, 2016 at 10:22
  • 1
    \$\begingroup\$ @Ehsan Oh. My condolence . \$\endgroup\$ Commented Aug 25, 2016 at 14:30
  • 1
    \$\begingroup\$ @Ehsan (later versions of ISE are still hardly usable in some aspects, but the pre-10 ISEs are really terrible, IMHO) \$\endgroup\$ Commented Aug 25, 2016 at 14:31
  • 2
    \$\begingroup\$ Installing a later version in a different place gives you the option of much better tools and doesn't uninstall or damage the old one (at least on Linux). And the option is there ... in the GUI, expand the list of commands under "Synthesis", it should be one of them. \$\endgroup\$
    – user16324
    Commented Aug 25, 2016 at 18:15

2 Answers 2

1
\$\begingroup\$

So I am not going to read the whole manual. But, from

XST manual

There is the option for "-rtlview yes", which tells XST to generate a netlist file representing the RTL structure of the design.

Direct quote: "You can also set this value in ISE® Design Suite in Process>Properties>Synthesis Options>Generate RTL Schematic."

There might be an option to print each reduced equation, but I cannot find it (I tried searching 'print' and 'equations', but there was no joy).

\$\endgroup\$
1
  • \$\begingroup\$ Wow! at least you opened my eyes to those hidden options. Thank you. I will read that Manual also. \$\endgroup\$ Commented Aug 28, 2016 at 3:17
0
\$\begingroup\$

For a CPLD I could find an option called "Fitter Report" which actually has an option to see the equation. But still can not find a similar option for FPGAs:

enter image description here

enter image description here

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.