# Why isn't this decoder being inferred as a LUT?

I'm trying to model a stack which has push and pop operations.

entity stack_256x16 is
Port (
push : in std_ulogic;
pop : in std_ulogic;
dout : out std_ulogic_vector (15 downto 0);
din : in std_ulogic_vector (15 downto 0);
clk : in std_ulogic);
end stack_256x16;


type operation is (OpNone, OpPush, OpPop);
signal op : operation;


In the architecture body:

op <= OpPush when (push = '1' and pop = '0') else
OpPop when (push = '0' and pop = '1') else
OpNone;


I just want to decode the push and pop inputs into an operation. One or the other can be set to do the expected operation. If none or both are set, do nothing.

I would expect something this simple to be implemented as a LUT. Instead when I open the elaborated design (RTL schematic view) I get this mess of muxes and logic. Why is this happening?

I'm using Xilinx PlanAhead 14.7 and a Spartan 6. The value of op is used as the selector into some muxes, which select and register various addresses & control signals.

• What makes you think fitting that particular statement in one LUT leads to the most efficient implementation of the whole circuit? Aug 26, 2016 at 12:32
• Fair point. I think I made incorrect assumptions about what level of optimisation would be performed and the way the schematic would be represented. The post-synthesis schematic is closer to what I was imagining. Aug 26, 2016 at 12:54
• RTL /= LUTs. Technology view may show several of the "RTL View" gates are rolled into one LUT. Aug 26, 2016 at 18:14

The RTL schematic shows you how it has interpreted your code. As you can see, it has the exact combination of AND gates and multiplexers that your code describes. If you want to know how it has mapped this into the FPGA resources, you need to look at the 'technology schematic'.