I'm trying to model a stack which has push and pop operations.

entity stack_256x16 is
    Port (
        push : in std_ulogic;
        pop : in std_ulogic;
        dout : out std_ulogic_vector (15 downto 0);
        din : in std_ulogic_vector (15 downto 0);
        clk : in std_ulogic);
end stack_256x16;

In the architecture head:

type operation is (OpNone, OpPush, OpPop);
signal op : operation;

In the architecture body:

op <= OpPush when (push = '1' and pop = '0') else
      OpPop when (push = '0' and pop = '1') else

I just want to decode the push and pop inputs into an operation. One or the other can be set to do the expected operation. If none or both are set, do nothing.

I would expect something this simple to be implemented as a LUT. Instead when I open the elaborated design (RTL schematic view) I get this mess of muxes and logic. Why is this happening? mess of muxes and logic

I'm using Xilinx PlanAhead 14.7 and a Spartan 6. The value of op is used as the selector into some muxes, which select and register various addresses & control signals.

  • \$\begingroup\$ What makes you think fitting that particular statement in one LUT leads to the most efficient implementation of the whole circuit? \$\endgroup\$ Aug 26, 2016 at 12:32
  • \$\begingroup\$ Fair point. I think I made incorrect assumptions about what level of optimisation would be performed and the way the schematic would be represented. The post-synthesis schematic is closer to what I was imagining. \$\endgroup\$ Aug 26, 2016 at 12:54
  • \$\begingroup\$ RTL /= LUTs. Technology view may show several of the "RTL View" gates are rolled into one LUT. \$\endgroup\$ Aug 26, 2016 at 18:14

1 Answer 1


The RTL schematic shows you how it has interpreted your code. As you can see, it has the exact combination of AND gates and multiplexers that your code describes. If you want to know how it has mapped this into the FPGA resources, you need to look at the 'technology schematic'.

Note that the technology schematic is hard to navigate unless you set the synthesis option 'Netlist hierarchy' to 'rebuilt'. Also note that the tools are likely to optimize your code in a ways that can be hard to understand when looking at the technology schematic. You may not easily be able to find the LUT that corresponds to just a particular line of VHDL code, as opposed to that line combined with previous and subsequent (in terms of the logic flow) lines.

  • \$\begingroup\$ I've run synthesis and opened the schematic for the synthesized design. That's more like the sort of thing I was expecting (well I was expecting something in between those two levels, but never mind). At least I understand a bit more about what the tools are doing now. \$\endgroup\$ Aug 26, 2016 at 12:56
  • 1
    \$\begingroup\$ @FusterCluck if the answer resolves your issue, you would normally mark it as correct by clicking the tick on the left. \$\endgroup\$
    – scary_jeff
    Aug 26, 2016 at 16:08
  • 1
    \$\begingroup\$ Even further: in an optimised design, one line of VHDL may map to multiple LUTs in different locations, and multiple lines of VHDL in different locations may map to the same LUT. \$\endgroup\$
    – OrangeDog
    Aug 26, 2016 at 17:06

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