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How to find out Vout in the following problems?

The threshold voltages are given as Vt. enter image description here

My approach :

  1. In the first problem, I assume two possible ranges of Vout - - - Vout>0.7 and Vout <0.7. Now if Vout >0.7V, the device will be off since Vgs will be less than 0.3V in that case. So, the output will stick to that voltage (some voltage above 0.7V). Now if Vout<0.7V, the device will be on. Now since nothing else is mentioned about the remaining circuitry to which the device is connected, I assume that there must be some stray capacitance at the output port, which will start charging by the drain current and Vout will increase. Now as soon as Vout exceeds 0.7V, the device becomes off and thus Vout will stick to that voltage i.e 0.7V. Here the second assumption i.e Vout<0.7V seems more accurate to me. But I am not sure about it.
  2. In the second problem, since |Vgs|>|Vt| for the lower pmos, it will be on. So, the same voltage 1V will appear at the drain terminal of the lower device or equivalently source terminal of the upper device. By the same argument we can say that the upper device is on and thus Vout will be 1V. These are my approach for the above two problems. Let me know whether they are correct or not.
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    \$\begingroup\$ What is your attempt to solve it? \$\endgroup\$ – winny Aug 26 '16 at 15:49
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This is not the way this site is to used. Because you have not shown your effort or attempt in solving it, I'll only give you hints for solving it.

Problem 1: It's an NMOS device. You should be able to recognize the nodes: Source, Gate and Drain. Now, the first step is to identify which mode of operation the NMOS is in. Hint: The gate and drain branches are tied. Figure out gate-source voltage. Use the the appropriate the drain-current formula and you're good to go.

Problem 2: If you are able to solve the first one using the hints I've given you, you'll be able to find out these:

  • The branches: Gate, drain and source
  • The device type: NMOS/PMOS.

Once you have identified them, try to find out their modes of operation. Hint is: The bottom gate-source voltage has more magnitude than the threshold (-1V). Consider the voltage between the branches joining the two devices to be some value Vx. Find its operation region and hence use the required drain current formula. Then, do the same for the upper device. Equate the currents.

That's a lot. Work out now and update here. You can say where you're facing the problem and what you did to over come it. Share it and one of us will definitely help you out.

Edit: Proceeding to finding a solution:

Problem 1: Here, in the NMOS device, the output is taken at the source. The drain and gate voltage are tied to the same potential level; therefore, the device is always in saturation. So, using the drain current formula for saturation region:

Id = kn(Vgs - Vt)^2 ; where kn= kn'*(w/L) called the gain factor; a constant.

Id = kn(0.7-Vout)^2 ; Vgs = Vg - Vs

Because Id is unknown, the value of Vout can't be obtained. But, you can observe their relation from a plot of Id against Vout, wherein Vout = 0V when Id is at a maximum value, and it decreases non-linearly to Id=0 Amp giving Vout= 0.7V.

You are partially right in the sense that the Vout can't go above 0.7V because as soon as 0.7V value is reached, the device turns off. Rather than saying OFF and ON, it'd a good initial practice to mention the operating region; hence, cutoff region here. Below 0.7V, the device is conducting and is always in Saturation region (ON is traditionally used for device in triode/linear region).

To give more insights: (Read this only after you understood the remaining part). No conditions are mentioned for the given device, hence body effect and channel length modulations should be taken into consideration. For the latter, multiply a factor (1 + λVds), where λ is the channel length factor. There's a beautiful limitation you'll realize, if you take body effect into consideration; the threshold voltage of the device increases with the increase in Vout, and thus the Vout will be limited to a voltage lesser than 0.7V. From here we can conclude that NMOS can't pass a good high!

Problem 2: May be you are oblivious of the fact that PMOS/NMOS also have some resistance associated with them; hence a voltage drop is obvious. If you carefully observe, the currents in the two transistors is equal and, if you consider the MOS devices to be completely identical, then they form a series resistance network. If you apply voltage divider, equal voltage should drop between both of these; 0.5V between each device. Hence, the voltage at the node joining the devices(Vx, as I considered) is at 0.5V and Vout should be 0V, to give a 0.5V drop at the upper MOS device.

Both of these questions demand more qualitative understanding of the MOSFETs than just knowing the basic mathematics surrounding them. Hope I cleared a bit, will help you if you still have any confusion.

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  • \$\begingroup\$ I have shown my approach now. Let me know whether they are correct or not. Thanks in advance. \$\endgroup\$ – sourav chakraborty Aug 27 '16 at 3:30
  • \$\begingroup\$ @souravchakraborty That's great. Check out the edit here. \$\endgroup\$ – electronics Aug 27 '16 at 8:54

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