Can someone explain me benefits of this design (found in Douglas Self's book) in comparison with "classic" npn-based long-tailed pair? What second stage actually does?
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3 Answers
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The second stage obviously provides additional voltage amplification. However, it has an additional function as well. The capacitor from collector to base provides the dominant pole compensation that makes the amplifier stable (in general from unity gain to very high closed-loop gain.)
Since this is likely an integrated op-amp, where capacitance take a lot of area, the compensation takes advantage of the Miller effect to multiply the effective capacitance by approximately the gain of the stage.
Also, the PNP input stage allows the common mode voltage range to get much closer to the negative rail. Could be useful for single-supply application.
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The 2nd stage takes the output of the diff pair and applies a lot of voltage gain. It also rolls off the high frequencies (the miller capacitor) so that negative feedback applied externally does not cause instability or oscillations.
An op-amp should have lots of open-loop gain, be stable (closed loop), provide a low output impedance and a high input impedance thus, the 2nd stage greatly enhances the gain whilst providing stability when negative feedback is added.
Regards the use of PNP transistors, this is of no consequence to what stage 2 does. An NPN input pair will still have a stage 2 but, it might be a PNP transistor.
answered Aug 26, 2016 at 19:07
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There is an additional task the second stage must fulfill: Correction of unsymmetry caused by the first differential stage.
The problem is that the npn current mirror cannot be fully symmetric (cannot provide two equal DC currents). The current through the most right pnp transistor (with the "-" sign) is larger than the current through the left pnp transistor. The difference is caused by the two base currents (IB1+IB2) of the current mirror npn transistors.
However, balancing the currents through the diff. amplifier is important for the performance of the diff. pair. That means: Without any input signal, the quiescent DC currents of the pnp´s should be equal!
Now - this problem can be solved when the current gain and the operational point of the second-stage npn transistor is selected properly: Its base current must be identical to (IB1+IB2). In this case, the quiescent DC collecor currents of both pnp transistors can be made equal. Then, the diff. stage is fully symmetric and delivers a signal to the second stage which depends on the diff. input signal only.
EDIT(comment): There is an additional aspect - as far as the second stage transistor is concerned: Further improvement of symmetrical properties of the differential stage.
The collector-emitter voltage VCE1 of the left npn current mirror transistor is identical to VBE of the second stage transistor (app. 0.7V). Hence, we can assume that VCE1 is practically identical to the coll.-emitter voltage VCE2 of the other (right) current mirror npn transiustor (VCE1=VCE2=VBE2).
Therefore, the quiescent DC voltages VCE of both diff. stage pnp transistors are alo equal. This symmetry improvement eliminates variations that would result from larger voltage swings within the diff. stage as well as at the collector of the second stage transistor (VCE only ap. 0.7V).
