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I have a design which includes two modules, one that transmits parallel data to a UART_TX module, and the UART_TX module outputs the data serially. The data transmitter uses a state machine to output different data every time using an 8-bit bus. It looks something like this:

enter image description here

When the send pin is '1' the transmission starts. Of course it's way more complicated, as the two modules need to synchronize between them.

I am connecting the FPGA to an outside device which is supposed to respond when getting the data from the UART, but it doesn't.

In a Modelsim simulation everything is well so I am having trouble understanding what is wrong. I have also already used to exact same UART_TX module and it worked with the same outside device (but a bit different design) so I know for sure the problem is not with the UART module.

I would like to use SignalTap in Quartus to monitor the tx_out pin, but I don't know how, since I can only see the monitored pins for a limited period of time (unlike a simulation, where you can see what happens after 10us, 20us, 40us and so on). Is it possible to do that? Can I know what my output is?

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To capture data for long periods of time with SignalTap you have (at least) two options available:

1) Transitional

2) State

http://quartushelp.altera.com/14.1/mergedProjects/program/ela/ela_about_storqual.htm

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