# JK flip-flop timing diagram positive edge triggering

Welcome I would like to ask you for explain this timing diagrams. I got some assignments for reading timing diagrams and solved it but I am not sure if it is good.

I have JK flip-flop which is positive edge triggering (from low to high). Here is task If I am not wrong the input is only J and K = 0 right?

Here is my solution Guys, what do you think about it? Is it good?

Firstly, you should not see if it is a 'good' or 'bad' output, it should seem 'correct'.

This is how I see your question: It seems the INPUT port is your 'J' port, which is being given the signal; and you are expected to come out with the output value for the given change in J.

Because it is positive edge triggered, the output value will change only at the positive edge transition with respect to its output value in the previous clock cycle. I'll consider the following JK-flip flop truth table. Let's analyze it for each clock edge.

CLK edge 1: The output was initially zero (or to be precise, high impedance) and at edge1, INPUT = J = 0. So, the output should be zero in this clock cycle.

CLK edge 2: The output in the previous cycle was zero and INPUT= 0 at edge2. Again, the output in this cycle is zero.

CLK edge 3:
The output in the previous cycle was zero and INPUT =1 at edge3. For J=1, the output is 1, for both K=0 or 1.

CLK edge 4: The output in the previous cycle was one and INPUT= 1 at edge4. For J=1, the output will toggle to 0 if K=1, or it will remain at 1 if K=0.

CLK edge 5: The output in the previous cycle could be 1 or 0, depending on the value of K. If output was 1, similar case of CLK edge 4 applies. If output was 0, for INPUT = J = 1, the output becomes 1, for both K=0 or 1.

I think that cleared enough. I have assumed K is not connected to any control input, hence the output values depend on it in certain clock edges. If the question was supposed to mean that INPUT is given to both J and K simultaneously, then choose the case accordingly. Let me know if you have any confusion.

• Well, the picture in this exercise isn't enough clear because it looks like K isn't used. If you could, please tell me why CLK edge 1's output was zero? Should is be zero or one? – rusiano Aug 28 '16 at 9:23
• When a flipflop is switched ON from OFF state, all the previous data it had would be gone; hence called volatile memory. Hence, the output is taken to be in zero state even before the clock pulse is supplied. So, the output after edge1 would be 0, since J=0. Even if the output was '1' prior to the arrival of CLK edge1, the output after edge1 would've been zero; because J=0 and value of K(0 or 1) doesn't matter (check the truth table). – electronics Aug 28 '16 at 9:51
• Ok I see, thank you very much for help. You did great job man. – rusiano Aug 28 '16 at 10:14

Your output diagram seems correct to me, but I'm not sure whether it is clear to you what a J-K flip-flop is.

If I am not wrong the input is only J and K = 0 right?

Well, not really: as you can see in https://en.wikipedia.org/wiki/Flip-flop_(electronics)#JK_flip-flop, by setting $K=0$ you just put your flip-flop in the "set state", which means that its output $Q$ will constantly be $1$ (starting from the subsequent clock edge, of course), no matter what your input is. So, yes, the output you plotted is correct but it isn't your assumption of what "input" is.

I suppose that a more correct use of a J-K flip-flop would be to use one of the ports (let's say $J$) as a proper input carrying a signal from a circuit and using the other one (thus, $K$) as a control for what you want your output to be like (I assume you may want it to signal some conditions or events, or stuff like that).