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Im desiging a circuit with a binary counter which rates it's maximum count frequency in terms of load capacitance.

Im quite confused and having a lot of trouble wrapping my head around how to calculate this.

The input to the counter im using is a typical CMOS Inverter Oscillation Circuit shown here, with the output connected directly to the clock input of the counter.

The data sheet of the particular inverter im using specifies the input capacitance as 3.5pf, and the load capacitance of the crystal can be tuned (currently 8pf), but I cant work out how to determine what the total output capacitance of this circuit is? Which im assuming is what the load capacitance to the counter will be.

I plan to use a SN74HCU04 inverter and this binary counter. The binary counter specifies the maximum frequency in terms of load capacitance on page 6.

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    \$\begingroup\$ post data on all the stuff you're contemplating using, including the binary counter that rates its max fcount in terms of load C. Congrats on its rather than it's BTW :-) \$\endgroup\$
    – Neil_UK
    Commented Aug 27, 2016 at 11:21
  • \$\begingroup\$ Hi Neil. Thanks for your comment. I added the link to the binary counter and the inverter I plan on using. I dont have enough reputation to post more than 2 links at the moment. \$\endgroup\$
    – Nikoeng
    Commented Aug 27, 2016 at 13:43

2 Answers 2

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The CL on page 6 of your counter datasheet refers to the load capacitance on any relevant output of the counter. See page 8, section 7, that defines how CL is used. Notice how as well as defining a minimum fmax, there are two sections in each table for detailed propagation delays input to output for the different output loadings.

CL is there so that IC speeds are measured and specified in a reproducible way, that's appropriate for real life circuits.

50pF is a fairly typical industry standard loading, it's not far from a bit of trace, a bit of cable, and the 30pF of an oscilloscope input. Many manufacturers also quote into a lower capacitance like 15pF as it improves the timing, and is representative of a a bit of trace and a couple of CMOS inputs.

Your design breaks down into two independent sections.

The first is the oscillator. The crystal must see appropriate capacitances to ground on both its leads, in order to oscillate properly. Use the HCU04 specification to adjust those. Use another of the inverter sections to buffer the oscillator output, so the crystal only 'sees' one inverter load, and not whatever you are driving.

The second is the counter. As long as the buffered oscillator is producing a clean logic swing, and a frequency less than the fmax of the counter, you can connect the oscillator to the counter and can expect it to work.

The fmax of the counter is dependent on what sort of loads you want it to drive. If it's only a few logic gates, then use 15pF and fmax is 40MHz. If you want to load any output directly with an oscilloscope, then it may not work at 40MHz, and you'll need to drop to 25MHz. That's what x10 scope probes are used for, they drop the possibly 50pF of cable+scope capacitance down to the 10-15pF range.

You can always make the CL that your counter sees be less than 15pF by buffering the loads, if you find the load capacitance that you want to drive is excessive.

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  • \$\begingroup\$ Thank you! I now understand what the load capacitance is looking at. The output of this counter can be disabled, and set to a high impedance state. While counting I intend to disable and set the outputs to high impedance. In this case, do you think can I expect the load capacitance to be very low? My purpose it to be able to count at a rate of over 30MHz at 3.3v which, according to the datasheet requires a load capcitance of 15pf. The outputs of the counter will be connected to the inputs of a MCU GPIO inputs which rates them as having an input capacitance of 5pf per pin. \$\endgroup\$
    – Nikoeng
    Commented Aug 27, 2016 at 14:29
  • \$\begingroup\$ Using less than CL spec in datasheet implies you may exceed rated fMAX (min) or have margin. \$\endgroup\$ Commented Aug 27, 2016 at 14:48
  • \$\begingroup\$ The load capacitance must be less than 15pF, it does not require a load capacitance of 15pF. \$\endgroup\$
    – Neil_UK
    Commented Aug 27, 2016 at 15:15
  • \$\begingroup\$ Thank you both very much. It really helped me to understand. I meant to write less than 15pf in the previous comment. One last thing - if load capacitance is related to drive then if I disable the outputs (set to Z) of this counter while counting will the load capacitance will be effectively close to zero? I dont need to see the outputs while counting. \$\endgroup\$
    – Nikoeng
    Commented Aug 27, 2016 at 15:51
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From your additional info; you need to know the load capacitance for any output pin on the counter. Each driver has an RdsOn value by design that limits the current drive which affects slew rate = dv/dt = Ic/C This value also changes with temperature range, and self heating that comes from higher supply voltages. So you only refer to the datasheet, where it indicates no advantage to increasing Vcc.

To determine C_Load you need to add up all capacitance of connected loads and circuit layout. Then by interpolation of the datasheet specs you can estimate the absolute max f for a given supply tolerance and temperature range.

  • When there is uncertainty of CL then reduce Fmax with some margin.
    • keep in mind probe effects when testing, if necessary use a low capacitance buffer (~3pF Cin) for test verification to avoid interference.

enter image description here enter image description here There are two more implied questions. How to determine the maximum frequency of an inverter and how to choose the optimal accuracy of a crystal. You choose the maximum frequency of an inverter from the datasheet using a particular CMOS family, voltage and temperature tolerances. F can increase with high voltage and lower temperatures. These depending on your system tolerance specs. Next I will indicate how to choose the correct values of C once you decide what the frequency is that you want. The tuning range of a crystal is small because it's Q is very large >10k.

To chose the load capacitance C1 , C2 and C3 with the known values of C_in and Cp is the parallel rated load capacitance for crystal specified in the datasheet, then compute the series equivalent value of the total C on each side. The caps on both sides are in series thru ground across the Xtal as a parallel load resonant mode of oscillation.

If C2 is the fixed input load C_in then;

1/(C1+C_in) +1/C3 = 1/Cp

If the tolerance of the crystal is say 50ppm and you wish to null this tolerance to zero at25'C where Cp is defined, then C1 must have a certain tuning range above and below the value determined above to offset room temp. "tolerance" error to less than 1 ppm only at 25'C

"Stability" specs refer to total swing for in terms of ppm for a spec'd max/min temp.
For more details on AT cut crystals, search for the temperature curves which all are normalized to 25'C to zero. When a stable freq. is desired over temp, it is called a TCXO where temperature compensation of a varicap diode is chosen carefully with a Vc control voltage to match 3rd order family of curves designed for different temperature ranges which changes by the factory choice of cut angles in minutes or 1/60th of a degree.

These TCXO devices are now inexpensive with 1 or 2 ppm accuracy on inexpensive AT crystals to provide an active clock instead of having to design your own with great difficulty.

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  • \$\begingroup\$ Thank you for your in depth answer. It was very informative. Im sorry if I'm missunderstanding, but I allready have the load capcitances for the crystal I am using calculated and set. I am specifically trying to calculate the maximum frequency of the binary counter, not the inverters. The binary counter specifies its limits in terms of "load capacitance". Im having trouble getting my head around how to calculate the total load capcitance as seen by the binary counter. As I understand it, this would be the capacitance at the "out" point of the linked circuit. \$\endgroup\$
    – Nikoeng
    Commented Aug 27, 2016 at 13:52

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