Measuring continuous voltage and current circuit

I'm trying to make a circuit that measures continuous voltage and current of a power supply, so I'm controlling the load applied to it using a MOSFET controlled in a closed feedback loop. By varying the PWM duty cycle, that passes through a low pass filter (making a DAC), I can control the amount of load.

I thought the R4 resistor would be dissipating most of the power but actually it's the MOSFET that's dissipating most of the power source, so I decided to short circuit the gate, drain and source from the MOSFET with another MOSFET to divide the dissipation power but it started to gain some noise on the MOSFET back to the PWM source making it difficult to control the load.

Does anyone have a guess of what could be happening and how can I solve this problem?

as show in the figure below:

simulate this circuit – Schematic created using CircuitLab

• Please mention the voltages and currents involved with the power supply and load, like $20 V$, $1 A$ max, etc. – scanny Aug 27 '16 at 20:14
• What is your pwm freqency vs the RC filter cutoff? – MadHatter Aug 27 '16 at 20:30
• Scanny I want to be able to measure power supplies (V+) from 5 to 25V, with current varying from 1 to 5A. MadHatter the PWM's frequency is 490Hz. I decoupled the DAC signal from the amp op and the excursion looks very good varying from 0 to 12V with 0 to 100% duty cycle and it looks very linear. – Rinaldi Segecin Aug 27 '16 at 20:57
• Ok, that helps Rinaldi. So at 5V/1A (5W) a reasonably-sized heatsink in free air will work fine, and maybe so up to 10-20W depending on the heatsink. At 25V/5A (125W) you're definitely going to need a fan and maybe 2, 3, or 4 paralleled MOSFETs. The IRF530N says it can dissipate 70W, but that's with a heck of a fan on a generous heatsink. At that level you'd need to keep the test very short and probably not attempt with less than two parallel stages. – scanny Aug 27 '16 at 23:36
• Sorry for make you wait. – Rinaldi Segecin Aug 31 '16 at 20:17

The way these "electronic load" circuits are typically designed is to dissipate almost all of the power in the MOSFET and use the source resistor (your R4) in a current sensing role. Typically R4 would be 1Ω or 0.1Ω.

So, as WhatRoughBeast mentions, a heatsink is really a necessity, unless your current is in the small 10s of mA, and perhaps even then depending on the output voltage of the supply under test (which corresponds closely to the voltage drop across the MOSFET when R4 is low).

A large-ish resistor in the current sense role adds gain to the feedback loop (increases the loop gain), which moves the feedback circuit toward instability. Combined with the gate capacitance of the MOSFET, I'll be surprised if it's not oscillating already, even before paralleling a second MOSFET. Generally these electronic loads require compensation of the op amp circuit in order to be reliably stable. In any case, a large-ish R4 will make things worse, not better.

The typical way to increase capacity is to parallel the entire op amp MOSFET pair, going back at least to the non-inverting input. Due to the high impedance input of the op amp, I imagine one low-pass filter will serve just fine for two paralleled "load" stages.

But if the power you need to dissipate is under say 25 Watts, you can handle that with a heatsink and perhaps a fan for some active cooling.

If you really wanted to dissipate power in a resistor, you could place it ahead of the MOSFET. You'll still need a current sense resistor of course. Also, this limits the flexibility somewhat as far as the maximum current draw, but might be an idea worth exploring.

• scanny you're right about R4 I actually used 0.1 Ohms 10W there I wrongly put in the original post I'm sorry, I also used a heat sink and added another set of amp op combined with the mosfet but short circuited everything with their respective pairs perhaps I should leave the amp op's output separated and short circuit just the fet's drain, source, the amp op's inverting and non-inverting inputs. Thank you for the idea. I'll mount this Monday and get back here. – Rinaldi Segecin Aug 27 '16 at 22:25
• @RinaldiSegecin: The drain connections are shorted, of course, because they're both connected to the power supply unit (PSU) under test. But the source and op amp inverting node should not be shorted. You'll need a second current sense resistor. This is how load sharing (and some other things) are achieved. They are essentially two separate parallel load stages, connected at the non-inverting op amp terminal and MOSFET drains only (and ground of course). – scanny Aug 27 '16 at 23:31
• hmm ok. So estimating the load's current from the voltage on the power resistor would be possible just measuring just one of the amp op/mosfet association? – Rinaldi Segecin Aug 28 '16 at 1:08
• @RinaldiSegecin: Assuming the circuit is working correctly and your current sampling resistors are the same size, each parallel load path will draw the same current, within the tolerance of the sampling resistors. So the total load current would be $$I_{load} = n \cdot \frac{V_{Rsample}}{R_{sample}}$$ where $n$ is the number of parallel load paths. – scanny Aug 28 '16 at 2:06
• I mount the circuit with two mosfets with their own feed back loops and heat sinks and added a buffer after the "DAC" and the noise reduced considerably now it's much easier to control the load. I'd like to know how the feed back loop processes happens, but it's a topic for another post I guess. Thank you all very much. – Rinaldi Segecin Aug 31 '16 at 20:35

It's not a problem, it's the way the circuit works. Keep in mind that, when operating properly with negative feedback, the + and - inputs are essentially at the same voltage.

Now, once your "DAC" produces a voltage V, the same voltage V appears on R4. Since the current through the FET and R4 is the same, the power dissipated in R4 will be proportional to V, while the power dissipated in the FET will be proportional to (V+ - 4), and for V much smaller than V+ the power dissipated in the FET will be larger than the power dissipated in R4.

Your attempt to parallel 2 FETs was not horribly wrong, but different FETs have different gains for the same gate voltage, so one of the FETs is hogging most of the current, but in effect the gain of the composite FET varies with gate voltage, since if one FET is on and the gate voltage rises above the turn-on threshold for the other the amount of current will increase dramatically. This gain nonlinearity, combined with the capacitive loading on the op amp due to gate capacitance, is causing your op amp to become at least slightly unstable. This is made worse by high-frequency components of your PWM getting past the cap.

You are best off sticking with one FET, and putting a heatsink on it. You should also check the voltage across R4, and make sure that your op amp/FET is not oscillating, which will draw significantly more power than if it is well-behaved.

simulate this circuit – Schematic created using CircuitLab

Figure 1. Adjusting PWM between 0 - 10 V will result in 0 - 10 V on the feedback signal. Voltages are measured across R4 and M1.

Figure 1. Power calculation table for V+ = 20 V.

Figure 2. Graph of power in R4 and M1 vs PWM voltage. Note that for the range selected M1 dissipates more power than R4 as it is dropping more voltage. If we continued the chart X-axis up to 20 V PM1 would drop back to zero as the voltage across it reduces.

Does anyone have a guess of what could be happening and how can I solve this problem?

I don't understand what you have done with the second MOSFET but if you are referring to the heat dissipation problem then you have to realise that the combination of M1 and R4 is your test load - not just R4. The circuit is working and you need to cool M1 adequately.