How to integrate a signal in LTSpice?

Question

Is it possible to integrate a signal in LTSpice and plot the result?

Answer 1

Sure, you can use the idt function, for example with a behavioral voltage source, we see the integral wrt time of a sine wave with an offset.

Answer 2

Simply use a 'B' behavioural voltage source with the integral function.

V=idt(V(sig))

Where sig is (in this case) a node voltage signal you want to integrate.

You can gate the integral using either time or some system state. e.g. Using a node voltage called 'trigger'

V=idt( u(v(trigger)) * v(sig) )

or, using time as a gate

V=idt( (time > 1m & time < 3m) * v(sig) )

Or, using the reset parameter to reset the integral after 5 milliseconds

V=idt( (time > 1m & time < 3m) * v(sig), 0, time > 5m )

To plot the result, simply give the B source output a name and plot that name. If you want you can divide the 'voltage' by '1V' to make it unitless.

From the manual, there are two forms of integral:

1   idt(x[,ic[,a]])  Integrate x, optional initial condition ic, reset if a is true. 
2   idtmod(x[,ic[,m[,o]]]   Integrate x, optional initial condition ic, reset on reaching modulus m, offset output by o. 

Answer 3

Summary
Yes, it is possible to integrate a signal in LTSpice. Use .meas directive. To plot the integral use .step directive.

Details
Below is an example of how to calculate average charge supplied by a switched capacitor circuit as well as an average current flowing in it. To calculate the charge we integrate the actual current over one period. To calculate the average current we further divide the charge by the time period value.

Suppose, there is the following switched capacitor circuit. The period of non-overlapping clock signals \${\varphi _1}\$ and \${\varphi _2}\$ is 10n (clock frequency f is 100 MHz).

Let’s first calculate analytically the average charge and current flowing in the system:

$${Q_{one\_period}} = C \cdot (VDD - {V_{test}}) = 100fF \cdot (1V - 0.5V) = 50fC.$$ $${R_{eff}} = {1 \over {C \cdot f}} = {1 \over {100fF \cdot 100MHz}} = 100k\Omega $$ $${I_{average\_one\_period}} = {{VDD - {V_{test}}} \over {{R_{eff}}}} = {{1V - 0.5V} \over {100k\Omega }} = 5\mu A$$

Now, let’s get these analytical results in LTSpice.

Build the following circuit:

Code for the LTSpice directives:

.param P=10n
.param t=5n
.step param t 10n 40n 10n
.meas tran Charge_one_period INTEG I(Test) TRIG time VAL=t-P/2 TARG time VAL=t+P/2
.meas tran Average_Current_one_period  INTEG I(Test)/P TRIG time VAL=t-P/2 TARG time VAL=t+P/2

Notes:
a) P stands for integration interval, t are measurement points (10n, 20n, 30n, 40n).
b) Download link for the file cmosedu_models.txt (PMOS model P_50n used).

Now run simulation to see the actual current flowing in the circuit:

Not really enlightening, isn’t it?

However, if we use our directives:
View -> Spice Error Log -> RClk -> Select “Plot .step’ed .meas data” -> In an opened window RClick -> Visible waveforms and select the calculated data:

As one can see, the simulation result for the charge supplied and average current correspond to the analytical calculation above.

Answer 4

Without stealing @FakeMoustache's suggestion (and since the OP didn't specify), I'll just add, along his lines, that definite integration (the basic moving-average) is also possible:

Here, integration from 0 to 1 for a 1Hz raised cosine. Note that V(b) is plotted with a 0.1V DC offset, for better comparison. As seen, both methods yield the same result (V(a) and V(b)).

Despite the larger number of elements and nodes, the second suggestion may come faster and more orecise, as the tline has a fixed delay that is not dependent on the sampling rate (i.e. the simulation timestep). Of course, given the conditions, a simple behavioural source may be more convenient -- this is, entirely, a user's choice.