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Im using this SN74LV8154 binary counter, which specifies count frequency in terms of load capacitance (Page 6). The test circuit in the datasheet (Page 8) shows the load capacitance only on a single pin.

In a datasheet is the load capacitance specified as the sum of each output pin's load capacitance or is it the load capactiance of any single output pin?

In the latter case, does this mean that the maximum count frequency will be determined by the pin with the highest load capacitance?

Eg. If each 7 of the output pins are connected to an input capacitance of 5pf, and 1 of the output pins is connected to an input capacitance of 10pf does this mean the load capactitance (CL in the datasheet) will be:

7 outputs x 5pf + 1 output x 10pf= 45pf or just the maximum, 10pf?

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It will be the maximum load capacitance for a single output (i.e. per pin). Notice how the diagram specifies "from output under test".

Output under test

The capacitance is an important consideration in terms of maximum output frequency, which is governed by the time constant of the capacitance coupled with the resistance of the CMOS totem pole.

You shouldn't have an issue driving a 10pF load on all the outputs. CMOS inputs are typically higher capacitance than something like TTL, so the drivers are designed to cope with the higher capacitive load in order to be able to drive a reasonable number of inputs from the same output.

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  • \$\begingroup\$ Thank you. It makes sense to me that the switching characteristics for a single output would be affected by the load capacitance on that line but it seemed counter intuitive that the maximum internal count frequency would be affected only by the maximum load capacitance out of all the outputs. \$\endgroup\$
    – Nikoeng
    Commented Aug 29, 2016 at 2:16
  • \$\begingroup\$ It's a test condition, not a maximum load capacitance. If you have other capacitive loads in mind, you might want to do your own testing, though. \$\endgroup\$
    – Whit3rd
    Commented Aug 29, 2016 at 7:34

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