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I am currently studying flip-flops.
I understand the purposes of flip-flops, and that they can be made by using NAND or NOR gates.
But what are the reasons for making them these two ways? Does either way work for storing bits? Or is this just for cost consideration?
Even though the comments and the answers are quite reasonable, i would like to add some information that i assumed you didn't know based on your question
[CMOS]
Because all the CMOS circuits are complementary circuits you can`t build a CMOS AND gate, you will end up building a NAND followed by NOT gate to form this AND gate, this is because PMOS is used as pull-ups while NMOS is used as pull-downs. For more information you should look into This question. The figures below shows the CMOS implementation of the NOR,NOT and NAND gates
They both do the same logic function, but sometimes one of them is better than the other. Let me give an example
below are the NAND and NOR implementation for this logic function
One of the differences here is that A input in the NOR implementation is connected to only two transistors [NOT gate], while in the NAND implementation is connected to 4 transistors [2x NAND gates] which means that in the NOR version the A input have HALF THE CAPACITIVE LOAD than the NAND version
So in this example both versions differ in the loading on A input you might start worrying about this capactive load if for example A is connected to many other circuits
The gist is: depending on many factors one can decide which version is suitable for a circuit but both do the same function
Well, in practice flip flops are usually built at a transistor level with a highly optimized circuit as they are used all over the place and need to be as small and as efficient as possible. There are a number of ways of building a flip flop depending on the style of logic and the circuit requirements. One method is to use pass transistors and build something that somewhat resembles SRAM cells. Another method is to use dynamic logic where the stored value is actually stored as charge in parasitic gate capacitance, however this results in a minimum clock frequency requirement to continuously refresh the stored value.
I used to use S-R Flip-Flops made from NOR or NAND gates, depending upon what I was trying to accomplish with each particular design.
The simple way to think of it is this: a FF made from two NAND gates has active LO inputs. A FF made from two NOR gates has active HI inputs.
Ignore the technology behind those gates - this didn't matter for low-speed industrial systems. You get 4- dual-input gates in a 14 or 16 pin package and the goal was to minimise the package count while maintaining extremely-good reliability.
You could get your choice of AND, OR, NAND, NOR, XOR, XNOR. They all cost about the same per package. The goal was to minimise the total number of packages in the design.
Many of my designs were used in industrial settings. I would use FFs made from NAND gates so that the inputs were active LO - this allowed the use of standard "contact closure to ground" signals.
One other advantage to using NAND gates for FFs fed from external inputs: I would use cd4093 CMOS Schmitt-Trigger NAND gates with RC filters on the external inputs. This gave me extremely good noise filtering and the series resistor provided significant ESD and transient protection. Some of those designs were used for decades with no failures.
both NAND and NOR are universal gates because any circuit can be derived from these. so you can use either one but NOR is the better choice.
