Even though the comments and the answers are quite reasonable, i would like to add some information that i assumed you didn't know based on your question
Why NAND and NOR gates are the building blocks?
Because all the CMOS circuits are complementary circuits you can`t build a CMOS AND gate, you will end up building a NAND followed by NOT gate to form this AND gate, this is because PMOS is used as pull-ups while NMOS is used as pull-downs. For more information you should look into This question.
The figures below shows the CMOS implementation of the NOR,NOT and NAND gates
What is the difference between NAND and NOR versions?
They both do the same logic function, but sometimes one of them is better than the other. Let me give an example
below are the NAND and NOR implementation for this logic function
One of the differences here is that A input in the NOR implementation is connected to only two transistors [NOT gate], while in the NAND implementation is connected to 4 transistors [2x NAND gates] which means that in the NOR version the A input have HALF THE CAPACITIVE LOAD than the NAND version
So in this example both versions differ in the loading on A input you might start worrying about this capactive load if for example A is connected to many other circuits
The gist is: depending on many factors one can decide which version is suitable for a circuit but both do the same function