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Using CMOS technology, where tp=tHL=tLH=10ns, I need to make an simple circuit which generates square waves with frequency of 50MHz. I know that T=1/f = 20ns. I also have another formula that I found in a book and it says T = tHL+tLH = 10ns + 10ns = 20ns. I know how to convert logic gates to CMOS, but I don't know how to build this circuit using only logic gates, because of that frequency. The simplest circuit that I know, is that: 1 NAND gate, with one of it's inputs x = 1, and another input y = feedback of output.

EDIT: If I have 50 Mhz frequency and I want to divide it by 2 so it will be 50/2 = 25, is that possible with the circuit that I designed below? enter image description here

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  • \$\begingroup\$ I'll give you a hint: Google "ring oscillator" \$\endgroup\$ Aug 30 '16 at 12:01
  • \$\begingroup\$ yes ! this circuit is like using one NAND gate with one input x = 1, and 2nd input y = feedback of NAND output. But how does frequency work? \$\endgroup\$
    – Linksx
    Aug 30 '16 at 12:03
  • \$\begingroup\$ NAND gates ? Then you're not looking a the most simple one which is 3 inverters in series, see en.wikipedia.org/wiki/Ring_oscillator Consider that each gate has a 10 ns delay, how much time does it take for a signal change to travel the whole loop ? 3 x 10 = 30 ns so it will oscillate with a period of 30 ns. Now you can easily calculate the frequency. If you want a lower frequency, put 5 inverters in series or 7 or 9 or .. (2 or 4 or 6 will not work, why ?). \$\endgroup\$ Aug 30 '16 at 12:10
  • \$\begingroup\$ @FakeMoustache - 3-stage ring oscillator with 10 nsec delay will have a period of 60 nsec, not 30. Since OP needs 50 MHz, 1 stage is what is called for. It won't work well in real life, but I suspect this is homework. \$\endgroup\$ Aug 30 '16 at 12:35
  • \$\begingroup\$ @fakemoustache 2,4,6 will never work because will not oscilate \$\endgroup\$
    – Linksx
    Aug 30 '16 at 12:48
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The simplest circuit, given your data, is

schematic

simulate this circuit – Schematic created using CircuitLab

Look at the inverter. Assume, just for the moment, that the output is high. Since this is applied to the input, 10 nsec later the output will go low. 10 nsec after that the output will go high again, and the cycle repeats with a 20 nsec period, or 50 MHz.

As I commented, this won't work well in real life. The problem is that in addition to propagation delay a simple inverter will have limited slew rate, and when operated at these speeds it will not have time to settle at either logic level. Instead, it will probably give a pretty good sine wave output, and may not reach the full output levels you expect.

The NAND version is perhaps slightly easier to understand (or maybe not, depending on what gives you trouble). The problem with the inverter circuit is that, when thinking about it the first time, it's hard to see how the input and output can be the same, since this is an inverter. The trick, of course, is to think about the fact that this can only happen for one propagation delay, which is why it oscillates. The NAND version at least allows you to start with a 0 input on the control line, and then think about what happens when you bring it high. But the inverter is internally simpler than a NAND gate, so the inverter circuit qualifies as the simplest.

EDIT - It has been asked, "how about if we have 25 MHz frequency?", since doubling the delay around the loop requires 2 inverters, which won't oscillate. Right on. The answer is that you can't do it using only logic elements. Instead you do something like

schematic

simulate this circuit

where the values of R and C are adjusted to give the proper delay. As a rough estimate, the product of R and C should just about equal the delay required.

But why the second inverter, you ask? Well, the first inverter has a certain output resistance, on the order of 10s to hundreds of ohms. Any load capacitance (and all loads have capacitance) will create a secondary delay network,

schematic

simulate this circuit

and the output frequency will be exquisitely sensitive to things like printed circuit layout and wiring. Adding the second inverter provides a buffer which will stabilize the output frequency, and the effect of its input capacitance can be compensated for by modifying R and C.

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    \$\begingroup\$ I don't think that circuit will work properly (which you did mention). However I don't think it is necessarily related to the slew rate at the output, but because it will just settle with Vi=Vo=~ about half the supply voltage (with very very small oscillations around this center point). \$\endgroup\$
    – jbord39
    Aug 30 '16 at 13:39
  • \$\begingroup\$ @WhatRoughBeast Ok, I understood, but how about if we have 25 MHz frequency? if would be T=40 ns so we need to use 2 inverters, but if we use 2 inverters circuit will not oscillate so there will be no square wave. How can be this thing achieved? \$\endgroup\$
    – Linksx
    Aug 30 '16 at 14:07
  • \$\begingroup\$ @ClaudiuM: If you want to slow down the logic gates, you can always put a header/footer PMOS/NMOS in line with the power supply voltage. This will effectively increase the ON resistance of the pullup and pulldown path (slowing down oscillations). This forms a "stacked inverter or gate" which implies "weakened inverter or gate". It is a very common technique in VLSI (I commonly stack 3-4 FET's, but past that it gets dicey at low voltages). \$\endgroup\$
    – jbord39
    Aug 30 '16 at 16:36
  • \$\begingroup\$ @ClaudiuM - A more general approach is to use an RC network as a delay. See edit. \$\endgroup\$ Aug 30 '16 at 16:52
  • \$\begingroup\$ @WhatRoughBeast Thank you for explanations. I got it now. \$\endgroup\$
    – Linksx
    Aug 31 '16 at 6:53
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It will work if you use an inverting Schmitt trigger gate:

schematic

simulate this circuit – Schematic created using CircuitLab

(Our circuit editor doesn't seem to support Unicode to full extent).

There are practical circuits based on the same principle which use a quartz crystal or an RC circuit to define the desired frequency, rather than relying on delays in logic gates which change from chip to chip and even for the same chip in different conditions like PSU voltage or temperature.

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