I have a Serial-ATA Controller design working on almost any kind of Xilinx 7-series devices, except for the Artix-7 device, which gives me headaches...
The pure design (SATA 6.0Gb/s, 150 MHz design clock) can be implemented on my Artix-7 200T. If I add ILA cores (formerly known as ChipScope), the timing is not met.
What did I do the relax the situation: - added 2 pipeline stages in each ILA core - added 1 pipeline stage between GTP transceiver and the logic - used retiming, remap and wide placement as alternative implementation strategy
This images show the normal design flow. The ILA cores are far away from the SATAController (SATAC) and the 8-bit CPU (SoFPGA), but the controller still has failing paths (that's the only region with failing paths).
It feels like the Artix-7 is out of routing resources in some areas. How can I get a report indicating such a suspicion?
I also tried retiming, remap and wider placement strategies. The result is this:
The timing failure is almost the same...
P.S. The design uses only 178 of >300 BlockRAMs. I used Xilinx ISE to use almost every BlockRAM in other designs, but I never encountered such a behavior.