# LTC3106 solar harvester example - open drain on power good pin

The part of the circuit of interest is highlighted on the image. The block with the antenna is just some device being powered, not important for the question except for providing the generic Vdd, EN and GND pin. I'm trying to understand the concept of an open drain from the example.

The description of PGOOD states:

Power Good Indicator. Open-drain output that is pulled to ground if VOUT falls 8% below its programmed voltage. The PGOOD pin is not actively pulled to ground in shutdown. If pulled high the PGOOD pin will float high and will not be valid until 3.5ms after the part is enabled.

Assumption

The 10MOhm resistor connects V_out and PGOOD. My thoughts are that this serves as a pull up for the EN pin because PGOOD can only provide a fixed ground potential and is floating otherwise.

• Is this a correct assumption?
• What is open draining in this example?
• What current and voltage are used for calculating the pull-up resistor value?

I don't think I understand what you mean in your assumption, so I can't tell you if it's correct.

The way I think of an "open drain" is: there is a switch inside the IC that either pulls that line to ground, or doesn't pull it to ground. If the signal is to be low, the switch is on, shorting the line to ground, if the signal is to be high, the switch is open, letting it float up to the relevant voltage level. The output is reliant on the voltage rail that the pull up resistor is connected to and the value of the resistor. A very large resistor will mean that the line will take a long time to increase (due to a large resistor providing a low current to charge the parasitic capacitance of the signal line).

Hence, when you ask for "current and voltage" to calculate the pull up value, that isn't quite right. What you're really after is working out the pull up value based on the rise time you want and the capacitance of the signal line (including the pins of connected ICs, the data sheets are usually good at providing this). As a rule of thumb, the charge time is about 5 times the RC constant (5*R*C, where R is pull up resistor and C is the capacitance of all items on the signal line).

In this event, the open drain is on the PGOOD signal, which means that the signal is always going to be low until the rail you're pulling up to is high, and then it will only become high once the power rail you're creating here is within tolerance. As these signals don't need to be particularly quick, the resistors are quite large (often 10K) to reduce power consumption when pulled low. Calculating the resistor value is more critical when dealing with an open drain communication link, such as I2C (or version thereof).

Quick summary: Open drain is either pulled to ground when low, or left floating for high. The value of the pull up resistor is based on the rise time you desire and the capacitance of the signal line and devices on the signal line.

• So once it stopped being pulled to the ground the voltage on PGOOD raises to a level very close to Vout. The time it takes for it to get there is defined by the RC constant? – TheMeaningfulEngineer Aug 31 '16 at 16:49
• Correct. You could calculate how close if you know the resistance of the paths to ground, but it will be pretty much bang on. – Puffafish Sep 1 '16 at 9:54

Open drain means that the output is taken from the drain of a mosfet but the drain itself is not connected to Vdd. Hence, if the gate voltage is high enough and the mosfet is saturated, the drain will be a tenths of a volt above ground, and so it is effectively grounded. If Vg is low, though, the mosfet is in the cut-off region and the drain is disconnected from ground and since it is not connected to Vdd, it is floating.

MOSFET Nch outputs require pullup for logic level indication. The Switch is active only when sufficient supply is available yet more than 8% below threshold.

When an internal comparator turns off logic threshold MOSFET inside, PGOOD out is open circuit and pulled up with high R value.