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I designed a PCB a few months ago, and after prototyping we have found a short circuit between a via and an internal power track. For an unknown reason I didn't see this problem earlier and when I reopen the PCB layout file I still don't see any mark from Altium indicating this short circuit. What I have done to see this short is to un-tent the via which was tented.

Does anybody know why Altium didn't indicate this short circuit to me before? Normally I run the design rule check so I am a bit amazed that I didn't catch this one. I attached two screenshots of the issue I had. One screenshot is taken immediately after reopening the layout file, and the other shows the violation I got after un-tenting the via. I didn't touch any design rules between the two pictures (I just un-tented the via)

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I would guess you have your DRC (design rule check) set to only show shorts when the checker is run in BATCH mode. If you want to change this to also check in ONLINE mode you need to go to Tools --> Design Rule Check --> Rules To Check and check both boxes next to "Short-Circuit".

You need to make sure that the design rule check is set to report short circuit errors, and that you don't have any rules that tell it to ignore the errors.

It doesn't look like you reviewed your board a whole lot before submitting it. That's incredibly unprofessional and I'm not surprised you got this error. When designing PCBs it's always a good idea to not only check it yourself (with a long break between the initial design and when you review it again) but also have another PCB designer review it. For example, what's with that wacky bump in VDD_EXT_UG96?

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  • \$\begingroup\$ Well, I have tried to run the design rules check again a few minutes ago just after opening the PCB, and it doesn't detect it as short circuit. I have checked that the rules is well activated. In the report it reports 0 as short circuit. I can do a video for you if you want...The wacky bump is a track width of power avoiding a via. \$\endgroup\$ – chris Aug 31 '16 at 16:53
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    \$\begingroup\$ he meant the wiggle connecting to Vdd via lower left \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Aug 31 '16 at 17:06
  • \$\begingroup\$ @TonyStewart it is right it is not super pretty, but I don't think this is the topic here :) \$\endgroup\$ – chris Aug 31 '16 at 17:13
  • \$\begingroup\$ Agreed, that was a bit of a side topic, but I was using it as an example of why you should review your work before having the boards made. You should have caught the via error for the same reason you should have caught that strange wiggle. It's not exactly the topic, but it is an illustration. Could you add a screenshot of your via properties window? \$\endgroup\$ – DerStrom8 Aug 31 '16 at 17:16
  • \$\begingroup\$ here is a video I made a few minutes ago showing the DRC being settup and style not indicating this violation: google.com/url?hl=fr&q=https://www.wetransfer.com/downloads/… \$\endgroup\$ – chris Aug 31 '16 at 17:33

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