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I was reading from start the cmos inverter. I read inbetween the text that " load driving capability of cmos inverter is high.... as in when input is high(vdd) , the nmos can sink a relatively large load current"......how did they get to the intuition that it can sink relatively large load current? Is it because there is a low resistance path imageto ground at that time? how do you explain this intuition?

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  • \$\begingroup\$ Erm, yes. NMOS has a lower Rdson than PMOS. \$\endgroup\$ – Ignacio Vazquez-Abrams Sep 1 '16 at 6:22
  • \$\begingroup\$ To be more precise: when comparing similar size transistors in the same manufacturing technology, the NMOS will have a lower Rdson than the equivalent PMOS. This is caused by the difference in mobility between electrons (NMOS) and holes (PMOS). \$\endgroup\$ – Bimpelrekkie Sep 1 '16 at 6:38
  • \$\begingroup\$ CMOS is complementary with N & P ch switches on all outputs. The RdsOn is fairly symmetrical so sourcing and syncing currents tend to be same on most chips. The RdsOn has migrated from each genration of logic families from >15V logic at ~300 Ohms, 5V HC logic near 50Ohms and ALC 3V logic near 25 Ohms \$\endgroup\$ – Sunnyskyguy EE75 Sep 1 '16 at 6:55
  • \$\begingroup\$ And these complementary outputs are made by making the PMOS transistors about 2 - 3 times larger (Wider) than the complementary NMOS transistor. \$\endgroup\$ – Bimpelrekkie Sep 1 '16 at 7:11
  • \$\begingroup\$ i was not trying to differenciate between pmos and nmos in my question.....all I am asking is how in BOTH nmos and pmos(whichever is on, based on input) can it souce/sink ( ya both) LARGE amount of current. How did this Large thing come into picture? \$\endgroup\$ – user98208 Sep 1 '16 at 7:43
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The inverter is the topology with the highest driving capability.

The current a transistor can sink or source depends on its gate-source voltage. In the case of an inverter the gate-source voltage is maximized. If the input is high, the gate voltage is Vdd, and the maximum gate-source voltage of Vdd-Vss is obtained.

At the same time the gate-source voltage of the PMOS is zero because gate and source are at Vdd. Therefore the PMOS is completely turned off and the NMOS does not need to sink any additional current.

Making the PMOS about three times larger than the NMOS results in a sourcing capability that is about the same as the sinking capability. Again this is the most efficient configuration for the PMOS as well.

Class-D amplifiers for example make use of this fact and use a structure that is basically an inverter to drive the load to achieve a very high efficiency. In such applications, however, sometimes different topologies (e.g. two NMOS transistors) are used to achieve even higher performance. Of course this a very simplified view.

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