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hi guys, I was given a task on optimizing propagation delay of four inverters using cadence software. The circuit connection is shown in above figure. I was asked to change the ratio of w/l for pmos and nmos to get minimum delay. The length of pmos and nmos is 160nm. So, I just need to change the width of pmos and nmos. However, what should I put the value of width for pmos and nmos??

I need tphl=tplh (symmetrical cmos).I understood that the in order for tphl=tplh, the ratio of w/l pmos must greater than 2.5 w/l nmos. or any other suggested value?????????

Increasing the w of pmos: tplh will reduce Increasing the w of nmos: tphl will reduce

1)What is the suitable width value for each pmos and nmos considering length=160nm ? 2)Can the width of pmos/nmos smaller than length ie >>>> w/l= 48nm/160nm????or the width must be larger than the length of pmos/nmos??? 3)Since I am using cadence software to design,do I need to take in consideration of capacitance or other formula?

ps: I am not familiar with VLSI

  • \$\begingroup\$ Please take the time to properly format, punctuate, and proof-read your question... \$\endgroup\$ Commented Sep 1, 2016 at 16:02
  • \$\begingroup\$ You should look up the concept of "logical effort" en.wikipedia.org/wiki/Logical_effort : It is an incredibly useful and important abstraction used to size logic gates. It is also very commonly asked in interview questions. \$\endgroup\$
    – jbord39
    Commented Oct 1, 2016 at 16:26

1 Answer 1


Since you are working with Cadence you could use simulation to find an optimum.

Use a design variable WP for the width of the PMOS and WN for the width of the NMOS. Define a parameter k.

For the first inverter specify the width of the PMOS as WP and for the NMOS as WN. For the second inverter use k * WP and k * WN, for the third k * k * WP and k * k * WN, and so on.

Perform a parametric sweep for k from say 2 to 10 with an increment of 0.1 and evaluate the delay of your buffer. Plot the result and find the minimum.

For a more theoretical approach you find some information here.

  • \$\begingroup\$ In your solution you implicitly assumed that each gate should be sized as k, k^2, k^3, ... This is true, but it comes from the concept of logical effort. Since you did not mention that in your answer, the OP may be curious why you knew to choose these ratios. \$\endgroup\$
    – jbord39
    Commented Oct 1, 2016 at 16:28
  • \$\begingroup\$ @jbord39 - This was no assumption. The scaling is given in the OP's schematic. \$\endgroup\$
    – Mario
    Commented Oct 1, 2016 at 16:52
  • \$\begingroup\$ Ah okay, I didn't see that. \$\endgroup\$
    – jbord39
    Commented Oct 1, 2016 at 16:57
  • \$\begingroup\$ I would like to add @Mario, the last inverter can also be designed first i.e. the one which is driving \$C_L\$. As you said \$W_p = 2W_n = 2W\$. Then we just keep decreasing the size of inverter as \$W_p' = 2W_n' = \frac{2W}{a}\$, \$W_p'' = 2W_n'' = \frac{2W}{a^2}\$ and so on.. \$\endgroup\$
    – rsg1710
    Commented Nov 9, 2017 at 9:12
  • \$\begingroup\$ @Mario, I think both analogy are equally used, in my experience I have used the methodology I have mentioned. Last to first ; but I have seen the other way round as well \$\endgroup\$
    – rsg1710
    Commented Nov 9, 2017 at 9:15

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