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I need to charge and discharge a capacitor up to supply Voltage and down to GND level. Supply voltage of the system may change between 120V and 60V. Also, to drive capacitor charge/discharge switch, I need to use logic structures.

So, I thought, IGBT may be a good fit for my needs.

IGBT drivers

Commercial simple logic circuits(SR Latch, NAND, OR vs) mostly use 5V TTL. Low side IGBT can be driven with 5V easily, However, I need to provide VCC and VCC-5V for High side IGBT to drive:

Waveform

So this is my question: How can I provide that signal level(VCC - 5V Low and VCC High) with simple structures? Please be aware that potential difference between Gate and Source of the transistor should not be above 5V and also please avoid to suggest Schmitt triggers because driver is already kinda slow I don't want it to be any slower. Thanks in advance!

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    \$\begingroup\$ also please avoid to suggest Schmitt triggers because driver is already kinda slow I don't want it to be any slower Why would a Schmitt-trigger be slow ? Don't dismiss a circuit beforehand without a "proper" reason. But what you need is a levelshifter. You could take a resistive divider and switch the current through it from the GND side but that will be slow. How about using some isolated components. Make the Vcc / Vcc -5 V using an isolated DCDC converter. Switch the IGBT from that 5 V using an opto-coupler. Input of optocoupler can be at GND level as it is also isolated. \$\endgroup\$ – Bimpelrekkie Sep 2 '16 at 11:11
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A IGBT for the low side switch makes no sense here. It's easy enough to drive a low side NPN directly. The FET is more in the way than doing anything useful for you. It also increases the overall resulting saturation voltage.

If you're going to have a PNP doing the high side switching, it's probably easier to drive it directly too. You don't say anything about your speed requirements, so it's hard to tell what is actually needed. However, to turn on a PNP only requires drawing current from its base. A low side NPN current sink can do that in a controlled way and independent of the high side voltage as long as it doesn't exceed the NPN's voltage capability.

Here is a example of what I'm talking about:

Q1 is a switched current sink. To first approximation, the current it will sink is just a function of R1, and is independent of the PWR voltage. When Q1 is turned on, it will draw a predictable amount of current from the base of Q2, turning it on. R2 turns Q2 back off when Q1 is turned off. C1 speeds up the on and off transitions of Q1.

Consider the power dissipation of Q1 carefully. Most of the power voltage will be across it when it is on. It also therefore must be rated for the maximum power voltage.

How C1 speeds up Q1

When everything is off, the base and emitter of Q1 are at 0 V, and C1 is discharged. When the base is raised to 5 V, for example, the emitter will follow to about 4.3 V. In steady state, this 4.3 V across R1 causes a current, most of which comes from the collector of Q1. However, during the low to high transition of the emitter, C1 is charged up. This causes extra emitter current during the brief rise time. C1 causes a fixed charge to flow thru Q1, in addition to the step in current caused by R1. The output current in response to a input step therefore has a initial high value, settling quickly to the steady state value controlled by R1. This initial extra slug of current causes things to get turned on more quickly.

The real benefit of C1 is to turn off Q1 quickly. Consider everything at steady state with Q1 on, which means its base is held at the logic high level. If the base is lowered to ground instantaneously, then for a short time the B-E junction is actually reverse biased, since the voltage on C1 can't go down instantly. This short term reverse biasing of the B-E junction turns the transistor off very quickly.

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  • \$\begingroup\$ Can you please elaborate on how is C1 helping in speeding up the system? As I see the circuit now, to turn on the whole thing the emitter voltage must rise to some RI value and the cap, which initially is empty, slows down the process. And conversely when you starve Q1 base, R2 pulls the collector high asap while C1 discharges in R1, slowly lowering the emitter. I also fail to see how C1 changes things when you turn off the N transistor. Thankyou! \$\endgroup\$ – Vladimir Cravero Sep 2 '16 at 12:00
  • \$\begingroup\$ @Vlad: See addition to answer. \$\endgroup\$ – Olin Lathrop Sep 2 '16 at 12:44
  • \$\begingroup\$ Thank you Olin. Reverse biasing the BEj is something I could actually have seen... Looking more carefully. \$\endgroup\$ – Vladimir Cravero Sep 2 '16 at 12:48

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