Way way too generic
The transistor could be in a section you don't use so you will never know.
It could be in a section you use, but the fail condition could still appear to work only ever needed a zero there, it failed to a zero and that is fine, I didn't notice it until perhaps a firmware upgrade that used that transistor differently.
Or it could be in a place that you use and the failure can result in any number of possible problems that may appear to manifest themselves in many ways. It is not possible to expand here certainly since we don't know what part you are using and how large the almost unmeasurable number of possible outcomes are a drop in the ocean doesn't begin to cover the number of hypotheticals. It is not worth talking about generally, even in aerospace.
For COTS systems, there is nothing whatsoever to protect you; you might have software that covers the dense or risky things like RAM, a POST memory test kind of thing. But if the failed transistor is as you suggest in the processor core, then you have a brick, again drop in the ocean, not possible to make a POST that covers the possibilities and reports on them properly, not worth the effort of even talking about it. You toss the thing and get another. Now when making the parts things like RAM that are higher risk might have alternate blocks on the die that can be fused in using the BIST or other screen tests. Likewise some products are derived from other products, to go back in the day a 80486SX vs 80486DX. If the floating point unit failed during chip manufacturing test, you blow the fuse(s) to turn it from a potential DX into an SX and sell it that way.
Chip screen looks for and, with experience, covers more than say 99.99% of failures. Depending on the product there is expected to be one in some number of thousands or tens of thousands that fail down the road. That is just how it is.
Aerospace, radiation-hard in particular, flip flops are or were when you still had folks around who know how to build reliable stuff (they have mostly retired now) are triple voted, three sets of transistors per, if one bit fails or experiences a single event upset (which is the primary reason for the triple voting) then the other two dominate the vote. You could argue that you get the what-if-one-fails argument. But you don't triple vote everything combinational logic isn't; if it gets a hit it should settle out before latching into the next flip flop/bit. You also need much beefier transistors to deal with single event upset, and you also have more other material to deal with total dose to extend the life of the part before the whole thing dies from exposure. Decades of experience (all lost to the young-uns who grew up in the disposable age, make space trash instead of make one that always works). A single transistor failing is not a primary concern, single event upset, and latch-up are (which could/would lead to destruction if not handled) total dose, etc. Single point of failure along with MTBF are very important; the MTBF should be longer than the mission life, and no single point of failure should be able to go without detection and resolution. Two failures at once are not normally solvable (drop in the ocean).
With COTS you don't worry about a single transistor failing; it is all about averages/statistics. You start with experience and there are not that many foundries anyway and they know what they are doing. You follow the decades worth of experience in design, layout, design verification, testing, etc. And you most definitely expect a yield less than 100%, and then of the parts packaged and delivered you expect some percentage of those to fail in the field. If your customers are expecting COTS quality and pricing, but fault tolerant or military or aerospace grade parts, you just need to educate the customer that what they are asking for is an order of magnitude more in price and an order of magnitude slower in bandwidth/processing power. As well as an order of magnitude longer lead time.
RAM being dense is an area focused on a lot, not for a single transistor failure, but more for single event upset, one bit flipped. So ECC/EDAC are used, as mentioned in manufacturing there might be a BIST and an alternate bank that can be fused in. With things like flash and/or hard drives they are failure prone so beyond the view of the user there may be extra banks/sectors that can be marked bad and others swapped in. It is possible with RAM, but normally not as you don't use RAM the way you use non volatile storage, instead you use DIMMs for example and have the user replace them if/when they fail. Normally like the processor socket that is for upgrades or configuration choices, not because RAM fails at any great rate compared to other components on the board.