Edit: clarify that it's not individual state machines' state that is invalid, but the whole system's.
Reset signals are needed for systems containing state machines when there are invalid system states. Possible examples would be
- protocol engines that count bits: sender and receiver need to agree where bit 0 is.
- a computer is reset: now its interrupt handlers are no longer able to service interrupt requests, so no further requests should be generated.
Invalid states are entered either because the registers are set to random values during powerup, or because of bugs or external influence (e.g cosmic rays flipping bits).
The reset logic only needs to change those registers that have an actual influence on the external behaviour, so there is usually no need to define reset states for every register (although several modern FPGA architectures have a dedicated reset distribution network so no additional resources are consumed here).
For example, a processor design would guarantee only that the program counter would be set to the reset vector, and the execution mode set to supervisor mode. The user registers do not need to be reset, because boot code is expected to overwrite them anyway.
Whether your adder needs a reset signal depends on the way it is designed. A purely combinatorial adder doesn't have any state, so there is nothing to reset.
If the output is registered, you could add a reset that clears it to zero, but I'd normally clear it to
'U' to cause an error in simulation if that value is propagated to an output port.
If your adder has additional state (for example, there are adder designs that only have a single input port, and add the value there to their accumulator), then you'd need a reset to clear the accumulator. Whether that reset is connected to a chip-wide reset, or generated by the next enclosing entity depends on the design.