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While designing PISO (parallel in serial out) in Xilinx Vivado using Verilog, the output waveform of the behavioral simulation (RTL-level, pre-synthesis) shows correct (desired output) value but post-synthesis or post-implementation functional or timing simulation is showing some unexpected results. There is a high frequency noise present at the new clock(slow)at near both edges in the simulation which is the main problem. How to eliminate this noise now? Is there any way to debug post synthesis level netlist? I have included my source code as:

module PISOleft(
input clk, 
input rst,
input [3:0]din,

output reg dout, 

);

reg [3:0]temp;
reg [25:0]temp1;
reg slow1;
reg slow;



         initial
               begin
                   temp1=26'd0;
                   slow1=1'b0;
               end
           always@(posedge clk)
                    temp1<=temp1+1;
           always @(temp1)
                  begin
            if(temp1==26'b10111110101111000010000000)//clock divided by 50Mhz
                        begin
                         slow1<=slow1+1;
                         end
                     else
                         begin
                          slow1<=slow1;
                         end
               slow<=slow1;
                  end




  always @(posedge slow)       // speed
      begin
         if(rst==1'b1)         // condition
            begin
                 dout<=0;
                 temp<=din;
             end
         else
            begin
                dout<= temp[3];
                temp<={temp[2:0],1'b0};
             end
      end
  endmodule

The warning I am getting at synthesis is:

 [Synth 8-327] inferring latch for variable 'slow_reg'

The noise present at my new clock(slow) is shown: This is post synthesis simulation result

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  • \$\begingroup\$ Add that as part of the question by editing your question, not as a comment. \$\endgroup\$ – Marcus Müller Sep 4 '16 at 8:40
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To address your almost-entirely-different question from your edited question: you need to update the value of slow for every path through the always block. This means you must have an else for your if, even though you want the value to stay the same. You still must explicitly state slow <= slow as the stay-the-same case.

Additionally, your design uses multiple signals as clocks to flip-flops. You should make your counter-based slow-clock-creation a separate module and bring in only one common clock to your module. You want the non-clock, non-reset signal into/out of your module to all use the same clock signal for their flip-flops in any moderately complex system that needs to synthesize and operate reliably.

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  • \$\begingroup\$ Just now i found the problem. Actually there is the presence of a high frequency noise present just before the arival of my slow clock(nc) at both edges at the simulation(synthesis and implementation) of my PISO design. but can u please tell me how to remove this unwanted noise from design.@user2943160 \$\endgroup\$ – Ravi Tiwari Sep 6 '16 at 7:46
  • \$\begingroup\$ i am trying to make clock divider as separate module now. thanks@user2943160 \$\endgroup\$ – Ravi Tiwari Sep 6 '16 at 9:25
  • \$\begingroup\$ i tried by making separate modules but still noise is coming at post-synthesis and implementation of my design. help plzz \$\endgroup\$ – Ravi Tiwari Sep 8 '16 at 16:39
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You can't set the same reg from multiple always blocks. You will need to rewrite the module so that regs are only set from within one always block. The simplest way to do this is to use one always block to implement all of the logic.

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  • \$\begingroup\$ i made it using a common always statement(above is the code) but still problem persisting @alex \$\endgroup\$ – Ravi Tiwari Sep 5 '16 at 14:55
  • \$\begingroup\$ I count 4 always blocks \$\endgroup\$ – alex.forencich Sep 5 '16 at 17:17
  • \$\begingroup\$ actually, first two always blocks are just for clock divider circuit(for slow clock generation) and third is so that i can see my slow clock at output, the fourth one working as my main logic for PISO design @alex \$\endgroup\$ – Ravi Tiwari Sep 5 '16 at 19:26
  • \$\begingroup\$ Just now i found the problem. Actually there is the presence of a high frequency noise present just before the arival of my slow clock(nc) at both edges at the simulation(synthesis and implementation) of my PISO design. but can u please tell me how to remove this unwanted noise from design.@alex \$\endgroup\$ – Ravi Tiwari Sep 6 '16 at 7:46

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