I am learing VHDL and wrote the code for Full Adder as :

library IEEE;

entity FA1 is
port (
A: in std_logic;
B: in std_logic;
Cin: in std_logic;
Cout: out std_logic;
Sum: out std_logic
end FA1;

architecture Behavioral of FA1 is
signal s1,c1,c2 : std_logic :='0';


HA1: entity work.HA1 port map(A,B,c1,s1); 
HA2: entity work.HA1 port map(s1,Cin,c2,Sum);
Cout  = c1 OR c2;

end Behavioral;

My doubt is as all the statements are going to be executed concurrently, how are the signals in the architecture of FA1 handled, e.g how are the values of s1 and c2 cordinated between these two statements? In this example it is must that that HA1 must be executed before HA2. So how is this handled without using "process"?

Also in the line

HA1: entity work.HA1 port map(A,B,c1,s1); 
work is referred to as the directory in which we are files will be compiled. However I couldn't find any folder named "work" in the workspace.

  • 1
    \$\begingroup\$ work is a library, not a directory. How libraries are implemented doesn't matter as long as they obey the VHDL language requirements : which means they can map onto a directory (but usually don't). And your "direct instantiation" is fine, you don't have to use components as the answer suggests. \$\endgroup\$ Sep 4, 2016 at 10:24
  • \$\begingroup\$ @BrianDummond: I've now edited my answer removing the component instantiation part, since that was not a problem, as pointed out by MojoJojo too. \$\endgroup\$
    – DavideM
    Sep 4, 2016 at 10:43

1 Answer 1


As per the "concurrency problem", you need to have clear in mind that VHDL can execute instruction concurrently, but that not all instructions are executed concurrently at all times.

In practice, what VHDL does is executing an instruction as soon as one of its arguments changes (e.g. an assignment var1 <= var2 is executed as soon as var2 changes). Getting to your problem, HA1 will be executed when A or B vary, it will produce c1 and s1 as outputs and then, when s1 is produced (varied), HA2 will execute.

  • \$\begingroup\$ By valid, if it means working, yes it is producing correct output. \$\endgroup\$
    – Mojo Jojo
    Sep 4, 2016 at 10:22
  • 1
    \$\begingroup\$ VHDL doesn't have instructions, it has statements. Statements can contain expressions. Concurrent statements include block, process, concurrent procedure call, concurrent assertion, concurrent signal assignment, component instantiation and generate statements. Concurrent statements are elaborated into process or process and block statement equivalents. The order processes resume is not defined. The VHDL simulation cycle emulates concurrency. Scheduled signal updates occur before any process is resumed, any further signal assignment updates can occur no earlier than the next simulation cycle. \$\endgroup\$
    – user8352
    Sep 5, 2016 at 5:20

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