# Handling of temporary signals in concurrent environment

I am learing VHDL and wrote the code for Full Adder as :

 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FA1 is
port (
A: in std_logic;
B: in std_logic;
Cin: in std_logic;
Cout: out std_logic;
Sum: out std_logic
);
end FA1;

architecture Behavioral of FA1 is
signal s1,c1,c2 : std_logic :='0';

begin

HA1: entity work.HA1 port map(A,B,c1,s1);
HA2: entity work.HA1 port map(s1,Cin,c2,Sum);
Cout  = c1 OR c2;

end Behavioral;


My doubt is as all the statements are going to be executed concurrently, how are the signals in the architecture of FA1 handled, e.g how are the values of s1 and c2 cordinated between these two statements? In this example it is must that that HA1 must be executed before HA2. So how is this handled without using "process"?

Also in the line

HA1: entity work.HA1 port map(A,B,c1,s1);
work is referred to as the directory in which we are files will be compiled. However I couldn't find any folder named "work" in the workspace.

• work is a library, not a directory. How libraries are implemented doesn't matter as long as they obey the VHDL language requirements : which means they can map onto a directory (but usually don't). And your "direct instantiation" is fine, you don't have to use components as the answer suggests. Sep 4 '16 at 10:24
• @BrianDummond: I've now edited my answer removing the component instantiation part, since that was not a problem, as pointed out by MojoJojo too. Sep 4 '16 at 10:43