# How to transfer data from/to the I2S controller through AXI DMA

I'm doing a sound analyzing project on the Zybo board and I'm having hard time using the AXI DMA for transferring data from the I2S controller to RAM. I'm using the I2S controller from the Digilent's github which is actually a modified Analog Devices IP - the codec on the board is Analog's SSM2603. The IP is supposed to support the AXI DMA mode as well as the PL330 DMA (from the processing system) and there's also the possibility of direct register access. The Zybo base system example uses the latter. The I2S IP uses a 8x24 FIFO for each channel and I know it works with direct register access.

I am trying to do the data transferring "properly" with a DMA and as there are no PL330 examples to be found (at least not bare metal, which is what I'm doing), I'm trying to use the AXI DMA. However I can only get a few samples to the RAM. I don't really know if there's a problem in the I2S controller or in my configuration of the DMA, so I'd first like to know if I understand how the DMA works.

I'm basing my code on the Xilinx' interrupt DMA example, so I think the initializations and similar are done correctly. What I'm unsure of is the following: I start the S2MM (Stream to Memory Mapped - I2S to RAM) transfer with the number of bytes to be transferred and expect the I2S controller to only output data when it has it. So if I want to transfer 5 seconds of audio, I start the transfer of

5 * 48000 (sampling frequency) * 2 (channels) bytes.


For now I then wait for the interrupt in which a flag is set, so that I know the transfer has finished. I expect this to last 5 seconds but instead it happens in a couple hundred ms (I don't have an o-scope) and only a few samples arrive.

So is my understanding correct? Has anyone ever used this I2S IP with DMA?

## 1 Answer

Okay, it seems my understanding described in the question is correct. The AXI DMA does work as I described and the I2S controller also seems to work correctly. The problem was that I thought that once TLAST is asserted it resets itself and the transfer continues, when in fact it immediately stops. I should've read how AXI stream works.

So I needed to set the period register in the I2S controller higher (it is only 16 bits long, so I might make it bigger later). Now I have another problem with MM2S transfer, but that doesn't really belong to this answer.