I've looked at this similar question, but it does not provide the answer I'm looking for. The documents from Xilinx also confuse me and the diagram provided in the Implementation view of the Xilinx software does not cast much light on this question.
My interpretation of how routing is done inside an FPGA is like the following diagram:
When I say signals, I meant to say CLBs
At each intersection of the blue and orange wires, there is a switch that is set when the FPGA is programmed to connect the two wires, as illustrated in the picture by the "Connection Point" dot. Once a connection point is set the the entire length of the blue and orange wires will be active in the connection.
I don't think my interpretation is correct.