I've looked at this similar question, but it does not provide the answer I'm looking for. The documents from Xilinx also confuse me and the diagram provided in the Implementation view of the Xilinx software does not cast much light on this question.

My interpretation of how routing is done inside an FPGA is like the following diagram:

enter image description here

When I say signals, I meant to say CLBs

At each intersection of the blue and orange wires, there is a switch that is set when the FPGA is programmed to connect the two wires, as illustrated in the picture by the "Connection Point" dot. Once a connection point is set the the entire length of the blue and orange wires will be active in the connection.

I don't think my interpretation is correct.


Your interpretation is overly simplistic. Real FPGAs have a complex hierarchy of routing resources, some for local connections only, some for medium-range connections and some for spanning the entire chip. These structures have been developed over many years of studying application designs, trying to strike a balance between the area required for routing versus being able to support a wide range of application logic structures.

In Xilinx chips, for example, these resources are in the metal layers, and they connect to small blocks of active logic that function as small crossbar switches, allowing fairly arbitrary connections between the ports of each switch.

If you fire up Xilinx's floorplanning tool on your design, and zoom way in to the level of individual slices, you can start to get a feel for the actual physical layout of the chip and its routing resources. It's quite surprising how small the area is that's devoted to the actual slice logic that implements your applicaion. The vast majority of the chip area is devoted to the routing resources.

  • \$\begingroup\$ So basically, my interpretation has some merit, but it misses a large amount of detail. The reason behind my question is because I am trying to compare the routing resource cost between using the APB protocol (one address bus for read and write operations) and using the AXI4-Lite protocol (a separate address bus for read and write operations). I thought I could develop an equation and good estimation with my simplistic interpretation, but it seems out of reach after reading your answer. \$\endgroup\$ – Klik Sep 5 '16 at 18:38

In addition to the previous answers: Here is a detailed view to 4 switch boxes, each for one CLB with 2 slices each.

enter image description here


  • gray: unused wires
  • green: used wires
  • white: one selected wire
  • blue: used elements (LUTs, FFs, ...)
  • \$\begingroup\$ This is excellent! How did you generate this image? I would like to do this with my design to learn more!!! \$\endgroup\$ – Klik Sep 9 '16 at 17:37
  • \$\begingroup\$ You can use Xilinx ISE FPGA Editor for old Xilinx FPGAs or Xilinx Vivado (device view + zoom) for Xilinx 7-Series FPGA or newer. Lattice has also a device viewer. Altera should have a similar tool. \$\endgroup\$ – Paebbels Sep 9 '16 at 17:40
  • \$\begingroup\$ I use Xilinx Vivado and I don't see detail like this, I just see the CLB units and no wires... I will take a second look at this later and see if I've overlooked something. \$\endgroup\$ – Klik Sep 9 '16 at 17:45
  • 1
    \$\begingroup\$ You need to open an implementation, then Vivado shows the device tab. Then enable wires ("Routing resources", second button on the left side). Now you can zoom and zoom and zoom ... \$\endgroup\$ – Paebbels Sep 9 '16 at 17:50

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.