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One of TI's new regulators has a rather unusual footprint, with several pads (7-13 in this instance) requiring that the pad metal extend under the solder mask.

This is in contrast to the usual case where the solder mark starts some distance outside the pad, as is the case of pads 1-6, 14 and 15 in this instance.

What would be the purpose of having a footprint designed like this? My guess would be heat dissipation, but it would be far more common to have a centre pad in this instance.

Modified VQFN footprint Solder mask description

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  • \$\begingroup\$ I don't think it makes sense for heat dissipation. My guess would be for manufacturing this gives more consistent results. \$\endgroup\$ – PlasmaHH Sep 5 '16 at 11:30
  • \$\begingroup\$ Is there something to do with registration going on here: that the actual pattern produced may vary as the mask and metal don't line up exactly, or the mask openings produced are slightly larger than specced? \$\endgroup\$ – pjc50 Sep 5 '16 at 14:21
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    \$\begingroup\$ Anything that moves away from an unaccessible center pad is great though. \$\endgroup\$ – Passerby Sep 5 '16 at 21:26
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There are two ways of defining the "active" area of a surface mount footprint: SMD and NSMD - that is Solder Mask Defined and Non-Solder Mask Defined.

It is unusual to see both in one footprint, but certainly not impossible.

SMD pads effectively have a raised lip around the edge of the pad. This at times can have an advantage over NSMD pads for a couple of reasons:

  1. It can create an insulating seal around the pads reducing the possibility of solder bridges forming during re-flow
  2. It increases the mechanical strength of the pad since the mask helps hold it down
  3. It limits the surface tension pull-down of the component on large pads

It is only the larger pads that are SMD in that footprint. Those pads will typically have more solder paste on them, which means the possibility of that paste oozing out sideways and forming bridges. The solder mask basically forms a barrier around the pad reducing the possibility of those bridges forming and making the solder paste remain within the area of the pad during reflow. Also when the solder paste melts the surface tension will suck the component down towards the pads. The larger the pad the more force it exerts. With large pads it is possible for them to exert too much pressure thus pushing the solder paste out of the normal pads and making bad connections. By using SMD on those pads you limit how far down the chip can be pulled by those pads. The mask forms a cushion on which the chip sits so the other pins can then reflow properly.

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    \$\begingroup\$ I have seen the term "solder mask dam" being used for that. \$\endgroup\$ – PlasmaHH Sep 5 '16 at 11:33
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    \$\begingroup\$ Don't swear :P Yes, that is a good term. Likening it to a dam holding back the flow of solder paste. \$\endgroup\$ – Majenko Sep 5 '16 at 11:34
  • \$\begingroup\$ Well, you're more concerned about the flow of molten solder during reflow than the paste! Paste is pretty unlikely to flow far (though bump a board and oops, it gets messed up). /pedantic \$\endgroup\$ – user2943160 Sep 5 '16 at 20:48
  • \$\begingroup\$ @user2943160 Paste is solder! Solder is paste! Where do you think the solder comes from?! \$\endgroup\$ – Majenko Sep 5 '16 at 20:51
  • \$\begingroup\$ (I find this fascinating.) So, in OP's example, the pads/mask are being arranged such that the larger pads on the right, with their mask overlay, would pull harder on the part causing a larger gap between the part and pads on the left than would otherwise happen. Is that right? (I see the other answer suggesting it may be due to current draw design side effects.) \$\endgroup\$ – Ouroborus Sep 6 '16 at 3:51
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Looking at the current rating of the internal switches (3.6A) and the device pinout, the use of soldermask defined and non-soldermask defined pads seems to be correlated with one thing: the high-current paths. Control/status/feedback are all NSMD and referenced to the NSMD GND pad. The input, output, and inductor pads are referenced to PGND and are SMD. I conjecture that since pads 7 to 13 are on high-current paths, the footprint recommendation designer expected the pads to be connected to wide, heavy traces that could consume additional paste if NSMD pads were used. Thus, these pads are intended to have SMD openings to ensure consistent copper land sizes.

TI TPS63070 pinout for the QFN package

This conjecture seems reasonable given the example/suggested layout provided in the datasheet:

TI TPS63070 datasheet figure 49 EVM layout

With the switched inductor being on connected using the other side of the circuit board, the enlarged copper area to hold the vias for L1 and L2 would likely reduce the success rate for soldering those pads because the paste would spread over a larger copper area than desired. Thus, SMD openings for these pads contains the flowing solder and could reduce the defect rate for this component.

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