What is the exact order of execution to access SRAM using a multplexers?

Question

Hello Electrical Engineering community,

I am new to this community and indeed new to electronics So please be gentle, Thank You, In Advance...

I have 2 x Alliance Memory ASC4008 SRAM IC Chips, I think they are 512Kb size each.

I also have 3 x Texas Instruments SN74HC595 multiplexers (I think that is what they are called)

And I wish to write code that runs on the MCU that will allow me to read and write to the SRAM memory.

I wish to use the SRAM as a video buffer for a 1280 x 720 display

I am not sure if I will be able to write to the SRAM while the MCU is reading the SRAM video buffer and displaying it onto the screen (in a continuous cycle)

I wanted to write to one SRAM IC while the other was being read.

I am unsure of the exact steps to take to complete this action. I have no idea whether to:

1. shift the address into the multiplexer and then chip enable the SRAM and try to read the data out?

or

2. chip enable the SRAM then shift the address into the SRAM via the multiplexer and then try to read the data out?

I imagine the sequence would be:

1. Set SRCLR Low on 74HC595 chips (clear shift registers)
2. Set OE Low on SRAM
3. Set WE High on SRAM
4. Set CE1 or CE2 Low (which ever SRAM IC I want to access)
5. set SRCLR High on 74HC595 chips
6. Send Address 1 bit at a time to 74HC595 chips
7. When all 19 bits of the address have been sent to 74HC595 chips then set OE HIGH on the 74HC595 chips

At this point I no longer know what to do next, or even if my list of steps above is correct.

Please can someone educate me on the correct method of manipulating the pins in order to complete the read access properly.

I understand that if I get the sequence wrong then data will be lost or mixed up and in effect turn up as gobble-dee-gook.

I have tied the 74HC595 shift-register-clock pin and the storage-register-clock pin together to free up one pin, but if need be I can dispose of the programming interface and that will free up two pins so that I can use one for clock registers and then separate the shift register and storage register clock pins.

Finally, I did read the data sheets, but as I come from a programming background, its very difficult to understand.

ASC4008 Datasheet

SN74HC595 Datasheet

Answer 1

You are definitely "in over your head" with this project. An answer that is detailed enough to get you going would be far too long for the Q&A format we use here.

Using a pair of SRAMs as a double-frame video buffer is a decent idea, but you'd have to run them "flat out" to produce a 1280×720 (1 Mpixel) display. In terms of capacity, you'll only have 4 bits per pixel — 16 colors, like the RGBI scheme used in the original CGA. And in terms of the bandwidth required to read out the data, you'll have to run them at their full speed of 18 MHz (55 ns per cycle). 36 Mpix/sec is just barely enough to produce a 720i (interlaced) image at 30 fps.

A shift register to generate the addresses is definitely a non-starter. The serial data rate required would be insane. You'll need 5 packages of quad 2:1 multiplexers for the address bus, and four packages of octal bidirectional data buffers to steer the data to the right places. In addition, you'll need logic (counters, etc.) to generate the display timing.

It's definitely doable — any computer geek as old as I am has probably built a display controller pretty much like this. But you need to get a lot more experience with digital logic in general before you can tackle it.