I have a fully digital implementation of a PLL. The problem that I have is the white noise coming from the PFD (you can view it as input jitter). I would like to filter it a lot, but an implementation with a PI controller lead to a slope of just a -20 dB/decade of noise rejection coming from the PFD.

Is it possible to improve it? The constrain that I have is on the rejection of the VCO Noise, which should have a slope of about 40dB/decade below the control loop bandwidth

The digital model is composed by:

PFD = Kpfd

VCO (include a delay of 1 sample) = $$ \frac{Kvco * T_s}{z-1}\ $$

PI = $$ \frac{(K_p+K_i)*z - K_p}{z -1} $$ L = PFD * PI * VCO

The input noise rejection function is $$ \frac{L}{1+L} $$ The VCO noise rejection function is $$ \frac{1}{1+L} $$

The currently used values are Kp=1500, Ki=20, Kpfd=2600 and Kvco=0.15 with a Ts=250us. I would like to have a L/(1+L) response above the cut-off frequeny above -20 dB/decade

Thank you!

  • \$\begingroup\$ much is possible depending on the details. Post the details. \$\endgroup\$ – Neil_UK Sep 7 '16 at 11:50
  • \$\begingroup\$ what is stopping you from low-passing the forward path? \$\endgroup\$ – JMJ Oct 8 '16 at 16:49

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