Currently I have one 'adder' entity with two architectures: (1) RippleCarryAdder (2) CarryLookAheadAdder.
I put all the definitions in one single VHDL file as below:
entity adder is generic (N: integer := 16); Port ( Cin : in STD_LOGIC; x : in std_logic_vector (N - 1 downto 0); y : in std_logic_vector (N - 1 downto 0); s : out std_logic_vector (N - 1 downto 0); Cout : out STD_LOGIC); end adder; architecture RippleCarryAdder of adder is begin ... end RippleCarryAdder; architecture CarryLookAheadAdder of adder is begin ... end CarryLookAheadAdder
Using ISE 14.7 Xilinx I can see that the tool has difficulty to properly distinguish two architectures associated to 'adder' entity. It only recognizes the last architecture specified in the file (in this case 'CarryLookAheadAdder').
I guess there is something with file domain, or maybe some rules that govern the architecture declaration which I am not aware of. Strange that the VHDL documentation has not talked about multiple architecture and file structure. Should I use two files, and copy entity declaration in both of them? Can you point to a page that properly discusses multiple architectures format supported by Xilinx ISE? (for example configuration keyword is not supported and I have to resort to another format to bound architectures.)