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Currently I have one 'adder' entity with two architectures: (1) RippleCarryAdder (2) CarryLookAheadAdder.

I put all the definitions in one single VHDL file as below:

entity adder is
generic (N: integer := 16);
  Port ( Cin : in  STD_LOGIC;
      x : in  std_logic_vector (N - 1 downto 0);
      y : in  std_logic_vector (N - 1 downto 0);
      s : out  std_logic_vector (N - 1 downto 0);
      Cout : out  STD_LOGIC);
end adder;

architecture RippleCarryAdder of adder is
begin
  ...
end RippleCarryAdder;

architecture CarryLookAheadAdder of adder is
begin
  ...
end CarryLookAheadAdder 

Using ISE 14.7 Xilinx I can see that the tool has difficulty to properly distinguish two architectures associated to 'adder' entity. It only recognizes the last architecture specified in the file (in this case 'CarryLookAheadAdder').

I guess there is something with file domain, or maybe some rules that govern the architecture declaration which I am not aware of. Strange that the VHDL documentation has not talked about multiple architecture and file structure. Should I use two files, and copy entity declaration in both of them? Can you point to a page that properly discusses multiple architectures format supported by Xilinx ISE? (for example configuration keyword is not supported and I have to resort to another format to bound architectures.)

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  • \$\begingroup\$ This may well be a Xilinx limitation. One approach that ought to work (but Xilinx has had problems supporting something as basic as VHDL's libraries in the past, so may not) is to put entity and architectures in separate files (3 files). Then you can directly instantiate as Adder1 : entity work.my_ent(my_arch1) generic map () port map (); Otherwise, it might be time to learn configurations. \$\endgroup\$ – Brian Drummond Sep 7 '16 at 17:02
  • \$\begingroup\$ What is the alternative Xilinx? Can I use another VHDL compiler and still program Xilinx FPGAs? \$\endgroup\$ – Ehsan Sep 7 '16 at 17:08
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    \$\begingroup\$ First find out if it IS a problem. Depending on the FPGAs, Xilinx offers Vivado as well as ISE, and for some FPGA families you can select between the old (buggy) and new (different bugs) parser within ISE (via the "use new parser" option). If all else fails, Synplicity sells a version that targets Xilinx, so you can try a different set of bugs. \$\endgroup\$ – Brian Drummond Sep 7 '16 at 17:29
  • \$\begingroup\$ "Trying different set of bugs". Makes me laugh. lol Thanks. \$\endgroup\$ – Ehsan Sep 7 '16 at 17:35
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    \$\begingroup\$ I wish I was being cynical when I said that! ISE8 is WAY too old for this sort of work. It took till ISE12 or 13 before ISE supported VHDL libraries properly and even then, the GUI took a few more releases to catch up. Back in the good old days you could submit minimal testcases via the Webcase system, and Xilinx would accept them. My record was 8 Webcases open simultaneously, 5 of them resulted in bugs fixed in later revisions (mostly in ISIM, but one or two in ISE). As an academic user you may still have a channel to do that. \$\endgroup\$ – Brian Drummond Sep 7 '16 at 18:57
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  1. To use multiple architectures in a single entity, the structure you're looking for (I believe) is configurations. I could never make heads or tails of configurations, and the usage is arcane as best I can tell. Best of luck if you try it.
  2. The half-assed way of doing it would be to use an if generate statement with a generic parameter selecting which instantiation to use. This requires having seperate entities for each architecture, and third entity to act as a wrapper around the generate statement.
  3. The really lazy way would be to just directly instantiate your HalfAdder and RippleCarryAdder as seperate modules, and ignore the headache altogether.

I've never attempted any of this, and I haven't used ISE in years. I don't know if it does support funky configurations, and it honestly wouldn't surprise me if didn't. Like everyone else was saying, I'd suggest upgrading to Vivado

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Ok I think I got the right answer:

We can put 'entity' into a separate file and 'architecture1' into another file, and 'architecture2' again into another file. So we will ended up having 3 separate files. Here the order of compilation does matter. First the file that holds the 'entity' definition must be compiled, and then the architectures. Xilinx ISE has an option which allows you to set the order of compilation manually. Also we can put all three in one single file, entity comes first and architectures follow.

ISE 8.1i up to 14.7 does not properly support multiple architectures and configurations PROPERLY. The only setups that I got them right are:

  1. Vivado v2015.4 64-bit (Funny they needed 10 years to support basic VHDL features)
  2. GHDL with GTKWave: This setup also perfectly supports multiple architectures, even better that Xilinx tools! The only drawback was that I got 'limited stack size' error in Windows. I switched to Linux version and it worked fine.
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  • \$\begingroup\$ Which ghdl version? ghdl used to have a --stack-size=nnnn option, now deprecated. If you're already using ghdl-0.34dev, consider reporting this (make it clear it's a Windows version problem) with testcase at github.com/tgingold/ghdl/issues \$\endgroup\$ – Brian Drummond Sep 8 '16 at 14:18
  • \$\begingroup\$ For GHDL, I used an installer called: "ghdl-installer-0.29.1.exe" so I guess my version was old and still had this stack size bug. My GHDL on Linux is at version 0.33 and does not have that stack size issue. \$\endgroup\$ – Ehsan Sep 8 '16 at 14:31

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