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I'm building a Z80 machine from components, to talk initially to a PC via bit banged I/O through an FTDI USB cable, and I've little idea how best to avoid back powering the Z80 board from a 5V data in-line. Z80-to-PC data is working nicely, the reverse otherwise. I am a neophyte at this, from a coding background.

Z80 Bit Bang IO Schematic

(Not shown above, I've also had to add a hacky N4148 between U1 and the data bus line.)

The issue arises when I want to receive bits on the Z80 machine, sent by the PC:

Powering down the Z80 machine, it remains semi-powered from the 5V data line from the PC. I've spent hours and much searching trying to understand this. Most of the internet seems concerned about safely back powering Raspi and Arduino, but there were some finds:

Culprit: This seems to happen via my U1 AND gate: the SN74HC08N data sheet shows Absolute Maximum Ratings for input "clamp" current as (should not exceed) +/- 20 mA outside the voltage range 0 to VCC, VCC being 0 here (power off), which I gather means it can be inadvertently back powered from inputs. So current to the U1 AND's input is exiting via VCC line, back powering the board.

Fixes I can see/have tried:

  • Putting a second N4148 or better on the U1 AND gate's VCC to cap back powering at small mA. Tried, hides/solves the problem, but I can't imagine this is right?

  • Use a MOSFET/BJT to attempt to drive U1 only from VCC, sending FTDI data in to the gate/base. I'm not skilled enough to know whether this is any more correct than a diode.

  • Op-amp plus MOSFET (as in a related but distinct question) - I can follow along but is this really the usual way? This doesn't feel like a standard approach for a little 8 bit machine, but perhaps I'm dead wrong.

  • Opto-isolation - this comes up a lot in answers from what I can see, but I'm not aware if this is standard practice for your average consumer device? Was every common 8 bit RS-232-capable microcomputer really opto-isolated? Schematics I've found seem to simply use the MAX232 or equivalent, but I can't work out how that helps.

How in your experience does one tend to avoid this when designing such circuits?

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    \$\begingroup\$ The current is not clamped; that value is for the current that flows through the voltage clamping diodes. And the absolute maximum ratings specify the values beyond which the device might blow up. \$\endgroup\$ – CL. Sep 8 '16 at 8:28
  • \$\begingroup\$ @CL Good point, I hadn't understood that properly. I'll update the question. \$\endgroup\$ – El Zorko Sep 8 '16 at 16:54
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Add a series resistor such as 10K to the input signal line only, which will limit the current without slowing down the signal too much.

Unrelated, but you may wish to add a 100K pullup to establish a known logic level when the FTDI cable is unplugged.

schematic

simulate this circuit – Schematic created using CircuitLab

There are certain logic chips that do not have the same kind of internal protection network and can be connected directly to an input voltage even when unpowered, but it's not necessary here.

Another approach is to simply insert a BJT with a 10K base resistor, which inverts the signal. If you put an 1N4148 from base to emitter, it can withstand huge transients or ESD on the input without frying anything.

schematic

simulate this circuit

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  • \$\begingroup\$ Thanks, this is a great explanation, and thanks for the note on the pullup as well. I've added the series 10k and that does indeed appear to solve the problem - I'm still getting some back powering, but of the order of 1V so not enough to light LEDs or run ICs. Would it be good practice (or pointless) to add a 1N4148 to the AND gate's VCC also? \$\endgroup\$ – El Zorko Sep 8 '16 at 14:23
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    \$\begingroup\$ It won't make any difference to the back-powering but it will avoid using the internal protection network. A BAT54 would be even more effective because it's a Schottky and has lower drop. A single BAT54S would allow you to clamp to both rails. Is it good practice? Probably, since otherwise you are breaking the datasheet rule about maximum input voltage, but it does not seem to be necessary so long as the current is limited to something reasonable such as 0.5mA. Without the resistor etc, applying a voltage to the input, then applying power, can cause the chip to fail due to latchup. \$\endgroup\$ – Spehro Pefhany Sep 8 '16 at 15:29
  • \$\begingroup\$ I'll look into that, thanks - looks like I can do some genuinely interesting reading there. Accepting this answer gratefully. Side question if you happen to have time: in the second approach, I follow that at those resistances, the BJT will act as a switch to pull down VCC, so inverting the signal w.r.t. the input. I presume the pull down is to avoid a floating signal when the input line (PC) is powered down. How does the use of the N4148 work here - is that somehow encouraging ESD to "loop" locally around the segment of the ground rail between R2 and Q1's emitter, or avoid entering the BJT? \$\endgroup\$ – El Zorko Sep 8 '16 at 15:58
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    \$\begingroup\$ Yes, the 100K is to prevent it from picking up noise if the wire is left open. The 1N4148 is not required for functionality, but it protects the transistor if < -5V is applied (maybe through ESD or a real RS232 port) to the input. You can leave it out most likely, but it really makes the input bulletproof against most abuse. \$\endgroup\$ – Spehro Pefhany Sep 8 '16 at 17:08
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Send a BREAK signal on the asynch interface from the PC to reset the Z80, this will set the TX data to idle which will be 0V on a TTL level interface.

Some PC communications software, some USARTS and some USB to ASYNCH converters are unable to hold the BREAK condition permanently but usually are able to cause a long (many character lengths) pulse and this should be enough for your circuit to reset.

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