I'm quite new to electronics and I'm having a hard time understanding the "pull-up resistor" principle. I have read a lot of articles about that, and I think I've got it but I'm not 100% sure so I have a question. In this article, after the first image, it says:

When the momentary button is pressed it connects the I/O pin to Vcc and the microcontroller would register the input as a high.

But I don't get it. Where is VCC? From what I see, there is no power source on this schema, just a microcontroller wired to a button that are both wired to ground so how can there be any voltage at all in this circuit?

  • \$\begingroup\$ I think they are referring to images 2 and 3 when they mention Vcc those images have VCC. \$\endgroup\$ – axk Sep 7 '16 at 19:15
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    \$\begingroup\$ Remember that U1 is a logic gate, which implies power and ground connections on the actual IC. These are not drawn in order to simplify the circuit diagram. \$\endgroup\$ – Ryan Griggs Sep 7 '16 at 19:16
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    \$\begingroup\$ I would say it's a mistake in the article. Once the button is pressed, it is connecting the gate input to a GND, not to Vcc. \$\endgroup\$ – Eugene Sh. Sep 7 '16 at 19:23
  • \$\begingroup\$ I agree with Eugene, it's a lousy article. Find a better source. \$\endgroup\$ – pipe Sep 7 '16 at 19:34
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    \$\begingroup\$ It appears that the author of that paper may have changed his mind between making the drawing and writing the text. It should say "... I/O pin to Ground, and the NOT gate would register the input as Low." That whole paragraph is generally confused. \$\endgroup\$ – Peter Bennett Sep 7 '16 at 19:37

The article seems quite confusing: the text and figures don't match. I'll try to present here the same three schematics as there, with hopefully a more matching explanation.

Assume U1 is your microcontroller, and P1 is an I/O pin configured as input. (It could be any logic gate, really.) Other connections to U1 are not that relevant so are not pictured, but assume it has power connections and other necessities.

(1) If the button is pressed, port P1 is connected to ground, and will sense a low logic level. But when the button is released, the port isn't connected anywhere, but is floating. There's no definite voltage present, so even minor noise may cause the digital input to switch from one value to the other. It might also oscillate, and cause increased power consumption. Not good.

(2) Now, when the button is not pressed, the port will sense a high level, since it's connected directly to Vcc. But if the button is pressed, Vcc is short-circuited to ground, and the power source will probably burn and die. Even worse.

(3) Here, if the button is not pressed, the port will again sense a high logic level: it's pulled high through the resistor. (There's no voltage loss over the resistor, since the impedance of the digital input is very high, and therefore the current to the port is approximately zero.)

When the button is pressed, the port is connected directly to ground, so it senses a low level. Now, a current will flow from Vcc to ground, but the resistor will limit it to something sensible. This is good.

In this schematic, an unpressed button reads as a high value (1), and a pressed button reads as low (0). This is called active-low logic. Swapping the resistor and the switch would invert this, so that an unpressed button would read as low (0), and a pressed button as high (1). (active-high logic.)


simulate this circuit – Schematic created using CircuitLab

  • \$\begingroup\$ i think this is a good explanation for a beginner to electronics to understand the topic. +1 for diagram and simple language. \$\endgroup\$ – Mark Ch Sep 7 '16 at 20:46
  • \$\begingroup\$ So if I understand you correctly, the thing that I neglected is the fact that U1 is actually connected to Vcc, being why in the first schematic, if the button is pressed, a current can go through? A second question, when you say in the point 3 that "but since the input impedance of a digital I/O port is rather high, it doesn't matter", you mean that 0 current at all will go to P1 or a current so small (because of the impedance of the input) that it will almost be equal to 0 => low level? Thanks for the nice explanation anyway! I mark your post as an answer because of the schematics :-p \$\endgroup\$ – ssougnez Sep 7 '16 at 22:19
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    \$\begingroup\$ "may not sense"... We say that the input may "float", and meander across a range of potentials. The pull-up resistor pulls the input "high". NB. the current does not matter (yes it is small), only the voltage. Things get a little more complex for circuits subject to "race" conditions. \$\endgroup\$ – mckenzm Sep 8 '16 at 3:28
  • \$\begingroup\$ @mckenzm I get it now. And you said that what matters is the voltage, so it means that surroundings noise could create a tension high enough to put the gate in a high state? \$\endgroup\$ – ssougnez Sep 8 '16 at 5:42
  • \$\begingroup\$ Or just the manufacturing process, this is very common for the embedded chips on credit cards now. The readers have pull up resistors. It's a point of failure now and then. \$\endgroup\$ – mckenzm Sep 9 '16 at 2:47

A pull-up or pull-down resistor "holds" the input at a specific level when there is no input to the pin, instead of allowing the input to float.

When you consider Figure 1 in your drawing, having the switch open provides no electrical connection to the pin, thus allowing stray interference, internal leakages etc to influence the voltage of the input pin. These external influences can cause the input to be interpreted as a fluctuating value, causing unwanted oscillation or unexpected output.

So, to ensure the pin is held at a "known" state, it needs to always be connected to either VCC or GND. See figure 2. However, there is a problem: if you connect the pin to VCC to hold it in a "high" state, then connect your switch to GND and press the switch, you create a direct short! You will either blow the fuse, damage your power supply, burn something, etc.

So instead of connecting the input directly to VCC or GND, you can connect the input through a pull-up/pull-down resistor. In figure 3, they use a pull-up resistor, connecting the input to VCC.

When there is no other input on the pin, almost zero current flows through the pull-up resistor. So there is very little voltage drop across it. This allows the entire VCC voltage to be seen at the input pin. In other words, the input pin is held "high".

When your switch is closed, the input and pull-up resistor are connected to GND. Some current begins to flow through the pull-up. But since it is a much higher resistance than the wire leading to GND, almost all the voltage drops across the pull-up resistor, causing ~0 volts to be present at the input pin.

You would select a relatively high value resistor to limit the current flow to a reasonable value, but not too high to exceed the internal resistance of the input.

Pull-up resistors allow you to hold the input at a known state when no input is present, but still give you the flexibility to input a signal without creating a short.

  • \$\begingroup\$ Thanks for this explanation, it is really clear. I had a lot of answers to this thread and unfortunately, I can only select a single one as the accepted answer. I chose another one because of the schematics of it but yours is also very clear. I upvoted it. \$\endgroup\$ – ssougnez Sep 7 '16 at 22:20

The article is confusing but here's the gist. The inverter has a high input impedance and shouldn't be left floating as it could assume a logic 0 or logic 1 or oscillate between the two.


simulate this circuit – Schematic created using CircuitLab

  • (a) Without a pull-up we would require a change-over switch to alternate between Vss and GND (ground). This arrangement would switch the input firmly one way or the other but there is a problem during changeover of the switch contacts when the input is floating momentarily. This could cause it to oscillate in the presence of electro-magnetic interference (EMI), for example.
  • (b) solves two problems: it uses a simpler switch and in the absence of switch closure the input is pulled high. When the switch is closed the input is pulled low.
  • (c) shows the same arrangement in inverse. Switch open pulls low.

The arrangement in (b) is more common as many IC logic devices have internal pull-up resistors resulting in lower component count and PCB area when using this arrangement.

Note that power and ground are assumed in many schematics. In the case of logic gates, for example, there is a common Vss and ground connection for 2, 4 or 6 logic gates. It wouldn't make sense to show them for each gate so they are assumed or shown separately with their accompanying decoupling capacitors elsewhere on the schematic.

  • \$\begingroup\$ Thanks for this nice answer. I have a question about something you said though. "The arrangement in (b) is more common as...". Isn't it "a problem" to have a pull-up resistor instead of a pull-down? Indeed, the pull-up will always draw current until the button is pushed and we can assume that most of the time, the button is not pushed, so it would mean that the circuit would draw current while it is inactive. \$\endgroup\$ – ssougnez Sep 7 '16 at 22:25
  • \$\begingroup\$ @ssougnez: Rather than post questions as comments, it's generally better to post questions as fresh new top-level questions -- or has it already been answered at electronics.stackexchange.com/questions/113009/… or electronics.stackexchange.com/questions/254037/… ? \$\endgroup\$ – davidcary Sep 8 '16 at 14:57
  • \$\begingroup\$ @ssougnez Either resistor will draw however much current the input pulls. And current will be drawn when the switch is closed, again, however much the input pulls. It depends what the input circuit looks like. \$\endgroup\$ – David Schwartz Sep 9 '16 at 4:17
  • \$\begingroup\$ @ssougnez: Some of this is for historical reasons. The inputs on TTL chips, for example, drew no current when left floating high. Pulling low drew some current. This meant that it was more power-efficient to pull low when required. Modern designs use FET based inputs which have the same input impedance when high or low so it doesn't make any difference. It's generally easier and more definite to switch to ground than to switch to positive supply - particularly when mixed voltage power rails are involved. \$\endgroup\$ – Transistor Sep 9 '16 at 6:54

Well, it's a NOT gate so I guess we're supposed to imagine an I/O pin connected where that LED is improperly shown without a series resistor. When you connect the input to ground, the output should go to Vcc (which may also be called Vdd, which is another story).

It's fairly normal to not show the power pins on logic gates. This is just to reduce clutter in the schematic. Note that the ground power pin on the logic gate is not shown either.

This gets a bit confusing (hiding the pins) when you have mixed logic voltages such as 1.8, 3.3 and 5V on the same board, so I don't do it usually myself, but it did save a bunch of clutter in the halcyon days when everything ran from 5V.


simulate this circuit – Schematic created using CircuitLab

  • \$\begingroup\$ Would it be possible, it it's not too much to ask to show me a complete example of this circuit ? I'd like to be able to correctly visualize the circuit without the pull-up resistor in order to be able too see the global picture. Thanks \$\endgroup\$ – ssougnez Sep 7 '16 at 19:22
  • \$\begingroup\$ See edit. Simplified internals of the inverter (usually more transistors for buffering and some protection diodes at least). The input will float around when the switch is not pressed, but when it is pressed the output is definitely high (M1 is on and M2 is off). \$\endgroup\$ – Spehro Pefhany Sep 7 '16 at 19:33
  • \$\begingroup\$ Wouldn't the I/O port to the right in your schematic be pulled to some known voltage through the LED instead of being actually floating? I think the article refers to the input of the NOT gate when it says "I/O pin". At the text after Figure 1, it just confuses Vcc with ground GND. After Figure 2, they are the right way again. \$\endgroup\$ – ilkkachu Sep 7 '16 at 19:58
  • \$\begingroup\$ No, the LED won't affect the voltage enough to worry about (it will still be a logic 1 or logic 0). As I said initially, I don't think it refers to the NOT gate input. It's not a microcontroller and it's only an input not an I/O pin, but really the page is not all that clear for a beginner. \$\endgroup\$ – Spehro Pefhany Sep 7 '16 at 20:15
  • \$\begingroup\$ Thanks, it's clearer now thanks to your answer and all the other ones. I upvoted yours ;-) \$\endgroup\$ – ssougnez Sep 7 '16 at 22:27

Pull-up or pull-down resistor are meant to fix a logic level (0 at GND or 1 at VCC). The resistor has higher impedence that the button. When you press the button, the level can change (if wired correclty).

The "not gate" representing the MCU in the figures is very basic and author ommited the VCC supply. Of course in figure 2 and 3 Vcc is present and well connected.

The sentense you picked was to explain the "active high" logic. The one corresponding to figure 1 is

Using a pull-up resistor the I/O pin will normally see a logic high and when the button is pressed it will see a low


Since floating inputs on CMOS can leak to false input levels are be prone to stray noise, either a hidden input pull-up R in a uC input port with switch to ground or an external bias R to one supply rail Vdd or Vss and switch to the opposite rail.


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