Modelling transistor V_be and bulk resistance

Question

I'd like to calculate algebraically the DC behaviour of various bipolar transistor circuits that used matched pairs or quads (exponential converters, current mirrors etc.), taking into account the imperfect matching between transistors and deviations from exponential behaviour. The aim of this is to see when cheap matched pairs (e.g. DMMT3904W) will suffice for a particular application, and when precision parts (e.g. SSM2212) are required.

Two of the parameters specified for the above parts are the offset voltage and bulk resistance (\$r_{be}\$). In the context of an Ebers-Moll model, where the emitter current is given by $$I_e = I_s (e^{V_{be}/V_t} - 1)$$ how should I model these parameters?

• Should I model the offset voltage just by specifying a different \$I_s\$ for each transistor in the pair?
• As I understand it the bulk resistance is effectively a resistance in series with the base-emitter diode - but is the voltage drop across this resistor equal to \$r_{be}I_b\$ or \$r_{be}I_e\$?

Answer 1

The offset voltage can be modeled with different Is, as you suggest. The Rbe, usually, is dominated by Rbb (the base spreading resistance); in low-noise transistors (high beta) this will have less effect, so you might want to use beta-selected transistor pairs in order to make this parameter predictable. So, it's Ib * Rbb...

In transistors intended for high-ish currents (500 mA and up) it is not unusual to see deliberately added emitter resistance (it prevents hot spots). And, in PNP transistors (because N material has higher mobility) the Rbb value might be smaller than in NPN ones.

Two manufacturers may use the same name, but don't always make the same transistor. Even from a trusted manufacturer, a geometry or process change can happen without notice. It's safest to avoid using off-datasheet info.

Answer 2

The Ebers-Moll model does not include Bulk resistance as this is a chip design and process variable.

The bulk resistance of \$V_{be} =r_{be}I_b\$ is not given but from the device curves we know it is related by the chip size and it's rated power dissipation design due to thermal resistance, usually given by max of Ib*Vbe at DC for some temp. like 85'C.

Other bulk R's

The same is true for the saturated incremental rise of \$ \Delta V_{ce}/\Delta I_{ce} =r_{ce}\$ adopted by Diodes Inc in their datasheets and have ~ 100 patents on these devices, for super-low saturated Vce(sat) devices. These can be as low as many low RdsOn FETS (10~100mOhm) but tend to co$t a lot more than typical BJT switches. But useful when you need high speed, high voltage and low Vce and low junction capacitance.

Pd(rated)@ Tjcn vs ESR or Bulk R

I have often correlated diode ESR which is similar to above for all diodes ( incl LED's ) and can estimate the bulk resistance accurately from the device's power limitations rated at some acceptable temp rise (40~60'C), where ESR or \$r_{ce}\$ or \$r_{be}\$ can be estimated, if one knows the maximum Pd for that junction at 60~85'C (ballpark).

After all, Vce(sat) is just the difference between Vcb and Vbe, two PN junctions in saturation.

We often assume Vce(sat) around 0.2V for nominal currents but super-low sat. BJT switches can be << 50mV at high currents and in most cases, the rise in Vbe or Vce can be estimated using Ohm's Law. Also some devices for Vce(sat) can be well over 1V, which is always due to bulk resistance in the design.

Note that Vce(sat) is always defined for Ic/Ib=10. i.e. base current using 10% of collector for standardized test methods. In better parts it may also be graphed for Ic/Ib=20 to 50. When designers mistakenly use hFE for switch designs instead of Ic/Ib = 20, give or take, then bulk resistance appears to rise due to lack of Vbe saturation or Ic/Ib ratio is too high.

• similar issue in MOSFETs but different mechanism

(p.s.) there is also a designer oversight in RdsOn ratios in cascaded switch designs with say 2 or more stages of FETs. the ratio of RdsOn for each stage is design factor just like the bulk resistance of cascaded BJT switch designs.

• e.g. don't try to make a SMPS with a 50 ohm CMOS driver on a FET with 5 milliohms this 10k ratio leads to excessive RC issues due to Ciss,Coss being inversely related to RdsOn)
• e.g. don't try to drive a 10A BJT with a 100mA BJT driver the ratio is too high.

After all, intuitively you know bulk resistance is related to size of the chip and a few other factors. I call all of these bulk R's , ESR and my formula is ESR=k/Pd where k is typically 0.5 to 1. ( lower k for better part designs like Cree power LEDs and Fairchild(TI)/Diodes Inc power diodes and hockey puck diodes)

This linear bulk resistance value is not specified in datasheets but is the primary wide tolerance value that is responsible for the wide tolerance on Vf for LEDs, Vce(sat) in BJT's and Vf @ Imax variations in ALL diodes. this tangent on the VI curve is often shown for nominal devices but then the Tables will show the Vf Min-typ-Max or Min-Max at the rated current.

This tolerance in bulk resistance is due batch-to-batch process tolerance stackup which is difficult to control for every wafer. Within any epiwafer, the tolerances are quite small relative to the whole production tolerance for high yields.

Notwithstanding, there is a NTC thermal temperature coefficient due to the Schockley Effect. So any Test Engineer will know that all datasheets standardize these curves at 25'C with pulses. Thus you will get a voltage rise with rising current due to bulk R but if inadequate heatsinking, then you get a reduction in voltage rise due to NTC Shockley effect ( which results in lower MTBF). Remember this when doing design verification.

In spite of many different supplier specs, for the same part, all must agree to the min-max values in the tables for Vf vs If or Vbe @Ib This essential limits the tolerances by JEDEC standards for generic part numbers for bulk resistance.

If you have any specific experiences on bulk resistance to share or do not understand what I am sharing, please detail in comments.