"Multiplexer controlled by configuration program" is a reference to how FPGA's work.
This multiplexer is not really part of your design. It's part of the configuration logic. Your design would instantiate a flip flop, either rising edge triggered or falling edge triggered(i.e: "if rising_edge(clk)" OR "if falling_edge(clk)", and the mux is the piece of logic that implements that.
The select input to the MUX that you don't see in the diagram is a single bit in the configuration bitstream that gets loaded/configured at power up.
Beyond that, there is no edge detection going on with the MUX. A MUX has no memory. In synchronous design, Edge detection requires 1 Bit of memory (i.e: the previous state: rising_edge_a <= a AND NOT previous_a). The Mux selects either an inverted or non-inverted clock to feed to the inherently rising or falling edge triggered(one or the other I'm not sure which) Flip Flop.