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The design is from a Xilinx FPGA doc. I think these are preprogrammed look up tables because there is no select bit input, but on the bottom it says they are:

Multiplexer[s] Controlled by Configuration Program

I'm not sure how to interpret that. The design sort of looks like an edge detector.

What is this and what is it doing?

enter image description here

Is it configurable to have the same functionality of these two circuits?

enter image description here

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2 Answers 2

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"Multiplexer controlled by configuration program" is a reference to how FPGA's work.

This multiplexer is not really part of your design. It's part of the configuration logic. Your design would instantiate a flip flop, either rising edge triggered or falling edge triggered(i.e: "if rising_edge(clk)" OR "if falling_edge(clk)", and the mux is the piece of logic that implements that.

The select input to the MUX that you don't see in the diagram is a single bit in the configuration bitstream that gets loaded/configured at power up.

Beyond that, there is no edge detection going on with the MUX. A MUX has no memory. In synchronous design, Edge detection requires 1 Bit of memory (i.e: the previous state: rising_edge_a <= a AND NOT previous_a). The Mux selects either an inverted or non-inverted clock to feed to the inherently rising or falling edge triggered(one or the other I'm not sure which) Flip Flop.

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  • \$\begingroup\$ Great answer. That actually cleared it up perfectly. I know in VHDL I can specify if the process should occur on a rising edge and I completely forgot about it until you mentioned it just now. So that is how the FPGA implements that part. Thank you! \$\endgroup\$
    – Klik
    Sep 9, 2016 at 17:48
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It looks like it allows the output flip-flop to be triggered by either the rising or falling edge of K (the clock signal), as selected by how you configure the multiplexer.

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  • \$\begingroup\$ It is a configurable edge detector... what is the benefit of that? \$\endgroup\$
    – Klik
    Sep 9, 2016 at 17:00
  • \$\begingroup\$ It's no edge detector. It's selecting if your FF is triggered by positive (rising) or negative (falling) edge. \$\endgroup\$
    – Paebbels
    Sep 9, 2016 at 17:05
  • \$\begingroup\$ @Paebbels Maybe I'm using the wrong terminology. I thought this was an edge detector. Is this the effect? A resulting short pulse, based on the configuration. \$\endgroup\$
    – Klik
    Sep 9, 2016 at 17:13
  • \$\begingroup\$ To your edit: No, your circuits use AND gates, but the FPGA has a multiplexer. That's a switch or as equation: \$y = \bar{s}a + sb\$ \$\endgroup\$
    – Paebbels
    Sep 9, 2016 at 17:35

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