I am working through the Quartus Prime Introduction Using Schematic Diagrams tutorial for Quartus Prime Lite 16. (I am using version 16.0.2 on Windows.) Because I have a DE1-SoC board, I specified that board and the corresponding device when creating the project:

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My circuit includes inputs named x1 and x2 and an output named f. In the assignment editor, I renamed SW[0] and SW[1] and the output pins LEDR[0], respectively, to my signal names. I ended up with:

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The pin assignments are shown in my circuit diagram:

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However, the assignments don't seem to be working correctly. I get these messages when I compile:

Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

Critical Warning (169085): No exact pin location assignment(s) for 3 pins of 241 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.

The fitter report includes:

210 LEDR[0] Missing location assignment

211 SW[0] Missing location assignment

212 SW[1] Missing location assignment

How do I assign signal names to pins correctly?


Here is the list of files for the project:

  • DE1_SOC_golden_top.sdc [which I did not manually create]
  • light.bdf
  • Waveform.vwf

When I double-click on DE1_SOC_golden_top.sdc, I get an error:

Can't open file DE1_SOC_golden_top.sdc -- file does not exist

I also see these messages when I compile:

Info (12021): Found 1 design units, including 1 entities, in source file light.bdf

Info (12023): Found entity 1: light

Warning (12125): Using design file de1_soc_golden_top.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project

Info (12023): Found entity 1: DE1_SOC_golden_top

Info (12127): Elaborating entity "DE1_SOC_golden_top" for the top level hierarchy

  • \$\begingroup\$ Make sure you are compiling the correct file. If it was previously exported to HDL, it may be using an old version of the schematic. Double check what module is set as the top level, and what files are included in the project \$\endgroup\$ Sep 10, 2016 at 0:59
  • \$\begingroup\$ You can also try closing and opening the project - sometimes the changes don't update until you force it to dump the assignments to file (closing and opening works, so does choosing "organise the quartus settings file" from the toolbar). \$\endgroup\$ Sep 10, 2016 at 1:06
  • \$\begingroup\$ @TomCarpenter Thanks for the suggestions. Unfortunately, reopening the project and organizing settings didn't help. The files also look correct. Might it matter that I made the changes to pins with Assignment Name "Location" and not "I/O Standard"? \$\endgroup\$ Sep 10, 2016 at 2:35
  • \$\begingroup\$ @TomCarpenter I added more information. \$\endgroup\$ Sep 10, 2016 at 2:41
  • 1
    \$\begingroup\$ If your top level schematic is named "light.bdf", you need to right click on that file in the project list and select the "Set as Top Level Entity" option, otherwise it won't know to use that file as the top level. I presume the current top level entity is DE1_SOC_golden_top which is no longer in the list of project files, but will still be in the project directory (file called de1_soc_golden_top.v), so it is using that one. \$\endgroup\$ Sep 10, 2016 at 3:41

1 Answer 1


The issue you are having is not the way you are assigning pins, that is being done correctly. The problem is in the file that is being used as the top level entity. The pin assignments apply only to the top level entity, and only code in that entity will be compiled.

According to the error messages, you have currently got a module called DE1_SOC_golden_top set as the top level entity which is declared in a file called de1_soc_golden_top.v. This file is not actually added to the list of project files (hence the warning), but will still be in the project directory so it is using that one. If the file didn't exist on the disk any more you would have got an error instead saying the module could not be found.

Your schematic is however called light.bdf which means you need to set the top level module to be light which is done by right clicking on the schematic file in the project list and selecting the "Set as Top Level Entity" option. Once you recompile the new top level module will be used.

  • \$\begingroup\$ Thanks a lot. I did set the top-level entity to light at the beginning, but that somehow got undone. All's good now. \$\endgroup\$ Sep 10, 2016 at 19:23

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